IS43R16160B-6TL INTEGRATED SILICON SOLUTION (ISSI), IS43R16160B-6TL Datasheet - Page 20

• Manufacturer Part Number: IS43R16160B-6TL
• Description: SDRAM, DDR, 16M X 16, 2.5V, 66TSOP2
• Manufacturer: INTEGRATED SILICON SOLUTION (ISSI)

Specifications of IS43R16160B-6TL

• Access Time: 0.7ns
• Page Size: 256Mbit
• Memory Case Style: TSOP-2
• No. Of Pins: 66
• Operating Temperature Range: 0°C To +70°C
• Memory Type: DRAM - Synchronous
• Memory Configuration: 4 BLK (4M X 16)
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS43R83200B
IS43R16160B, IC43R16160B
20
DDR SDRAM (Rev.1.1)
I
I
AC TIMING REQUIREMENTS
tDQSCK DQS Output access time from CLK//CLK
tWPRES Write preamble setup time
tDQSQ DQ Valid data delay time from DQS
tDQSH DQS input High level width
tWPRE Write preamble
Symbol
tDIPW DQ and DM input pulse width (for each input)
tDQSS Write command to first DQS latching transition
tDQSL DQS input Low level width
tWPST Write postamble
tRPST
tRPRE Read preamble
tMRD
tIPW
tQHS
tDSS
tDSH
tAC
tCH
tCK
tDH
tQH
tCL
tDS
tHZ
tHP
tLZ
tIH
tIS
DQ Output access time from CLK//CLK
CLK High level width
CLK Low level width
CLK cycle time
Input Setup time (DQ,DM)
Input Hold time(DQ,DM)
Control & address input pulse width (for each input)
Data-out-high impedance time from CLK//CLK
Data-out-low impedance time from CLK//CLK
Clock half period
DQ output hold time from DQS (per access)
Data hold skew factor (for DQS & associated DQ signals)
DQS falling edge to CLK setup time
DQS falling edge hold time from CLK
Mode Register Set command cycle time
Input Setup time (address and control)
Input Hold time (address and control)
Read postamble
AC Characteristics Parameter
Preliminary
Preliminary
CL=3.0
CL=2.5
CL=2.0
256M Double Data Rate Synchronous DRAM
tCHmin
tHP-tQHS
tCLmin or
-0.70
-0.70
Min.
0.45
0.45
1.75
0.72
0.35
0.35
0.25
-0.6
7.5
0.4
0.4
2.2
0.2
0.2
0.4
0.6
0.6
0.4
0.9
5
5
2
0
-5
+0.70
+0.70
+0.70
Max
+0.6
0.55
0.55
0.40
0.50
1.25
7.5
0.6
0.6
1.1
12
12
tCHmin
tHP-tQHS
tCLmin or
-0.70
-0.60
-0.70
Zentel Electronics Corporation
Min.
0.45
0.45
0.45
0.45
1.75
0.75
0.35
0.35
0.25
0.75
0.75
7.5
2.2
0.2
0.2
0.4
0.4
0.9
6
6
2
0
-6
A3S56D30/40ETP
+0.70
+0.60
+0.70
+0.70
Max
0.55
0.55
0.45
0.55
1.25
Integrated Silicon Solution, Inc.
0.6
0.6
1.1
12
12
12
tCHmin
tHP-tQHS
tCLmin or
-0.75
-0.75
-0.75
Min.
0.45
0.45
1.75
0.75
0.35
0.35
0.25
7.5
7.5
7.5
0.5
0.5
2.2
0.2
0.2
0.4
0.9
0.9
0.4
0.9
2
0
-75
+0.75
+0.75
+0.75
+0.75
Max
0.55
0.55
0.75
1.25
0.5
0.6
0.6
1.1
12
12
12
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
10/31/08
14
14
20
16
15
19
19
Rev. B