IS42S16160B-7TL INTEGRATED SILICON SOLUTION (ISSI), IS42S16160B-7TL Datasheet - Page 20

• Manufacturer Part Number: IS42S16160B-7TL
• Description: IC, SDRAM, 256MBIT, 143MHZ, TSOP-54
• Manufacturer: INTEGRATED SILICON SOLUTION (ISSI)

Specifications of IS42S16160B-7TL

• Memory Type: DRAM - Sychronous
• Memory Configuration: 32M X 8
• Access Time: 7ns
• Page Size: 256Mbit
• Ic Interface Type: Parallel
• Memory Case Style: TSOP
• No. Of Pins: 54
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S83200B,
FUNCTIONAL DESCRIPTION
The 256Mb SDRAMs are quad-bank DRAMs which operate
at 3.3V and include a synchronous interface (all signals are
registered on the positive edge of the clock signal, CLK).
Each of the 67,108,864-bit banks is organized as 8,192
rows by 512 columns by 16 bits or 8,192 rows by 1,024
columns by 8 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed (BA0 and BA1 select the bank, A0-A12 select the row).
The address bits A0-A9 (x8); A0-A8 (x16) registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information covering
device initialization, register definition, command
descriptions and device operation.
20
IS42S16160B
Initialization
SDRAMs must be powered up and initialized in a
predefined manner.
The 256Mb SDRAM is initialized after the power is applied
to V
with DQM High and CKE High.
A 200µs delay is required prior to issuing any command
other than a COMMAND INHIBIT or a NOP. The COMMAND
INHIBIT or NOP may be applied during the 200us period and
should continue at least through the end of the period.
With at least one COMMAND INHIBIT or NOP command
having been applied, a PRECHARGE command should be
applied once the 200µs delay has been satisfied. All banks
must be precharged. This will leave all banks in an idle state
after which at least eight AUTO REFRESH cycles must be
performed. After the AUTO REFRESH cycles are complete,
the SDRAM is then ready for mode register programming.
The mode register should be loaded prior to applying any
operational command because it will power up in an un-
known state.
DD
Integrated Silicon Solution, Inc. — www.issi.com
and V
DDQ
(simultaneously) and the clock is stable
07/28/08
Rev. D