IS42S16160B-7TL INTEGRATED SILICON SOLUTION (ISSI), IS42S16160B-7TL Datasheet - Page 25

• Manufacturer Part Number: IS42S16160B-7TL
• Description: IC, SDRAM, 256MBIT, 143MHZ, TSOP-54
• Manufacturer: INTEGRATED SILICON SOLUTION (ISSI)

Specifications of IS42S16160B-7TL

• Memory Type: DRAM - Sychronous
• Memory Configuration: 32M X 8
• Access Time: 7ns
• Page Size: 256Mbit
• Ic Interface Type: Parallel
• Memory Case Style: TSOP
• No. Of Pins: 54
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS42S83200B,
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown in
MODE REGISTER DEFINITION. The burst length deter-
mines the maximum number of column locations that can
be accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page
burst is available for the sequential type. The full-page burst
is used in conjunction with the BURST TERMINATE com-
mand to generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, mean-
BURST DEFINITION
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
07/28/08
Length
Burst
Page
Full
(y)
2
4
8
n = A0-A8 (x16)
n = A0-A9 (x8)
(location 0-y)
A 2
0
0
0
0
1
1
1
1
Starting Column
Address
A 1
A 1
0
0
1
1
0
0
1
0
0
1
1
1
IS42S16160B
A 0
A 0
A 0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
Type = Sequential
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
…Cn - 1,
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
Cn…
0-1
1-0
ing that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-A8 (x16) or
A1-A9 (x8) when the burst length is set to two; by A2-A8
(x16) or A2-A9 (x8) when the burst length is set to four; and
by A3-A8 (x16) or A3-A9 (x8) when the burst length is set to
eight. The remaining (least significant) address bit(s) is (are)
used to select the starting location within the block. Full-
page bursts wrap within the page if the boundary is reached.
Burst Type
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the
burst length, the burst type and the starting column address,
as shown in BURST DEFINITION table.
Order of Accesses Within a Burst
Type = Interleaved
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0
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