SAK-C167CR-L33M Infineon Technologies, SAK-C167CR-L33M Datasheet - Page 48

• Manufacturer Part Number: SAK-C167CR-L33M
• Description: 16BIT MCU, 2K RAM, ROM/ROMLESS, 167
• Manufacturer: Infineon Technologies

Specifications of SAK-C167CR-L33M

• No. Of I/o's: 111
• Ram Memory Size: 2KB
• Cpu Speed: 33MHz
• No. Of Timers: 9
• No. Of Pwm Channels: 4
• Digital Ic Case Style: MQFP
• Supply Voltage: RoHS Compliant
• Core Size: 16bit
• Oscillator Type: External, Internal
• Controller Family/series: C167CR
• Peripherals: ADC
• Rohs Compliant: Yes

C167CR
C167SR
Functional Description
3.13
Oscillator Watchdog
The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip
oscillator (either with a crystal or via external clock drive). For this operation the PLL
provides a clock signal which is used to supervise transitions on the oscillator clock. This
PLL clock is independent from the XTAL1 clock. When the expected oscillator clock
transitions are missing the OWD activates the PLL Unlock / OWD interrupt node and
supplies the CPU with the PLL clock signal. Under these circumstances the PLL will
oscillate with its basic frequency.
f
In direct drive mode the PLL base frequency is used directly (
= 2 … 5 MHz).
CPU
f
In prescaler mode the PLL base frequency is divided by 2 (
= 1 … 2.5 MHz).
CPU
Note: The CPU clock source is only switched back to the oscillator clock after a
hardware reset.
The oscillator watchdog can be disabled via hardware by (externally) pulling low pin
OWE (internal pull-up provides high level if not connected). In this case (OWE = ‘0’) the
PLL remains idle and provides no clock signal, while the CPU clock signal is derived
directly from the oscillator clock or via prescaler. Also no interrupt request will be
generated in case of a missing oscillator clock.
Data Sheet
46
V3.3, 2005-02