P89LPC916FDH NXP Semiconductors, P89LPC916FDH Datasheet - Page 42

• Manufacturer Part Number: P89LPC916FDH
• Description: MCU 8BIT 80C51 2K FLASH, TSSOP16
• Manufacturer: NXP Semiconductors

Specifications of P89LPC916FDH

• Controller Family/series: (8051) 8052
• Core Size: 8bit
• No. Of I/o's: 14
• Program Memory Size: 2KB
• Ram Memory Size: 256Byte
• Cpu Speed: 18MHz
• Oscillator Type: Internal Only
• No. Of Timers: 4
• Digital Ic: RoHS Compliant

NXP Semiconductors
P89LPC915_916_917_5
Product data sheet
8.19.5 Baud rate generator and selection
8.19.6 Framing error
8.19.7 Break detect
8.19.8 Double buffering
8.19.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)
Each enhanced UART has an independent Baud Rate Generator. The baud rate is
determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which
together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1
but is much more accurate. If the baud rate generator is used, Timer 1 can be used for
other timing functions.
The UART can use either Timer 1 or its baud rate generator output (see
that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The
independent Baud Rate Generator uses OSCCLK.
Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)
is ‘1’, framing errors can be made available in SCON.7 respectively. If SMOD0 is ‘0’,
SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON [7:6]) are set up when
SMOD0 is ‘0’.
Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the device
and force the device into ISP mode.
The UART has a transmit double buffer that allows buffering of the next character to be
written to SnBUF while the first character is being transmitted. Double buffering allows
transmission of a string of characters with only one stop bit between any two characters,
as long as the next character is written between the start bit and the stop bit of the
previous character.
Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is
compatible with the conventional 80C51 UART. If enabled, the UART allows writing to
SBUF while the previous data is being shifted out. Double buffering is only allowed in
Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled
(DBMOD = 0).
Unlike the conventional UART, in double buffering mode, the TI interrupt is generated
when the double buffer is ready to receive new data.
Fig 13. Baud rate sources for UART (Modes 1, 3)
baud rate generator
timer 1 overflow
(CCLK-based)
(PCLK-based)
Rev. 05 — 15 December 2009
8-bit microcontrollers with accelerated two-clock 80C51 core
2
SMOD1 = 1
SMOD1 = 0
P89LPC915/916/917
SBRGS = 0
SBRGS = 1
baud rate modes 1 and 3
© NXP B.V. 2009. All rights reserved.
Figure
002aaa897
13). Note
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