PIC16F872-E/SS Microchip Technology, PIC16F872-E/SS Datasheet - Page 260

• Manufacturer Part Number: PIC16F872-E/SS
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F872-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SSOP
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 22
• Interface Type: I2C/SPI
• On-chip Adc: 5-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PICmicro MID-RANGE MCU FAMILY
16.3.4
DS31016A-page 16-10
SSPIF
Interrupt flag
SCK
(CKP = 0)
SCK
(CKP = 1)
Master Operation
SDO
SDI
The master can initiate the data transfer at any time because it controls the SCK. The master
determines when the slave (Processor 2) wishes to broadcast data by the software protocol.
In master mode the data is transmitted/received as soon as the SSPBUF register is written to. If
the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed
clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal
received byte (interrupts and status bits appropriately set). This could be useful in receiver appli-
cations as a “line activity monitor” mode.
The clock polarity is selected by appropriately programming the CKP bit (SSPCON<4>). This
then would give waveforms for SPI communication as shown in
where the MSb is transmitted first. In master mode, the SPI clock rate (bit rate) is user program-
mable to be one of the following:
• F
• F
• F
• Timer2 output/2
This allows a maximum data rate of 5 Mbps (at 20 MHz).
Figure 16-3: SPI Mode Waveform (Master Mode)
OSC
OSC
OSC
bit7
bit7
/4 (or T
/16 (or 4 • T
/64 (or 16 • T
CY
bit6
)
CY
CY
)
)
bit5
bit4
bit3
bit2
bit1
Figure 16-5
1997 Microchip Technology Inc.
bit0
bit0
and
Figure 16-5