PIC16F872-E/SS Microchip Technology, PIC16F872-E/SS Datasheet - Page 273

• Manufacturer Part Number: PIC16F872-E/SS
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F872-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SSOP
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 22
• Interface Type: I2C/SPI
• On-chip Adc: 5-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.5
16.5.1
1997 Microchip Technology Inc.
SSP Module / Basic SSP Module Compatibility
Initialization
Example 16-2: SPI Master Mode Initialization
When changing from the SSP Module to the Basic SSP module, the SSPSTAT register contains
two additional control bits. These bits are:
• SMP, SPI data input sample phase
• CKE, SPI Clock Edge Select
To be compatible with the SPI of the Basic SSP module, these bits must be appropriately config-
ured. If these bits are not at the states shown in
be expected. If the SSP module uses a different configuration then shown in
Basic SSP module can not be used to implement that mode. That mode may be implemented in
software.
Table 16-4: New Bit States for Compatibility
Basic SSP Module
CLRF
CLRF
MOVLW
MOVWF
BSF
BSF
BCF
BSF
MOVLW
MOVWF
CKP
1
0
STATUS
SSPSTAT
0x31
SSPCON
STATUS, RP0
PIE1, SSPIE
STATUS, RP0
INTCON, GIE
DataByte
SSPBUF
CKP
; Bank 0
; Clear status bits
; Set up SPI port, Master mode, CLK/16,
;
;
; Bank 1
; Bank 0
; Enable, enabled interrupts
; Data to be Transmitted
;
; Start Transmission
; Enable SSP interrupt
1
0
Data xmit on rising edge
Data sampled in middle
Could move data from RAM location
SSP Module
CKE
0
0
Table
Section 16. BSSP
16-4, improper SPI communication should
SMP
0
0
DS31016A-page 16-23
Table
16-4, the
16