PIC16F872-E/SS Microchip Technology, PIC16F872-E/SS Datasheet - Page 657

• Manufacturer Part Number: PIC16F872-E/SS
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F872-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SSOP
• Package: 28SSOP
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 22
• Interface Type: I2C/SPI
• On-chip Adc: 5-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A.3
1997 Microchip Technology Inc.
Transfer Acknowledge
SDA
SCL
Condition
Start
S
All data must be transmitted per byte, with no limit to the number of bytes transmitted per data
transfer. After each byte, the slave-receiver generates an acknowledge bit (ACK)
When a slave-receiver doesn’t acknowledge the slave address or received data, the master must
abort the transfer. The slave must leave SDA high so that the master can generate the STOP con-
dition
Figure A-4:
If the master is receiving the data (master-receiver), it generates an acknowledge signal for each
received byte of data, except for the last byte. To signal the end of data to the slave-transmitter,
the master does not generate an acknowledge (not acknowledge). The slave then releases the
SDA line so the master can generate the STOP condition. The master can also generate the
STOP condition during the acknowledge pulse for valid termination of data transfer.
If the slave needs to delay the transmission of the next byte, holding the SCL line low will force
the master into a wait state. Data transfer continues when the slave releases the SCL line. This
allows the slave to move the received data or fetch the data it needs to transfer before allowing
the clock to start. This wait state technique can also be implemented at the bit level,
Figure A-5:
MSB
1
(Figure
Address
2
A-1).
Slave-Receiver Acknowledge
Data Transfer Wait State
acknowledgment
signal from receiver
Transmitter
7
Output by
Output by
SCL from
Receiver
Master
Data
Data
R/W
8
Condition
Start
S
ACK
9
byte complete
interrupt with receiver
Wait
State
1
clock line held low while
interrupts are serviced
1
2
not acknowledge
acknowledge
Data
2
8
Acknowledgment
Clock Pulse for
3 8
acknowledgment
signal from receiver
Appendix A
9
ACK
9
DS31034A-page 34-5
Condition
Stop
P
(Figure
Figure
A-4).
A-5.
34