SK-86R01 Fujitsu, SK-86R01 Datasheet
SK-86R01
Specifications of SK-86R01
Related parts for SK-86R01
SK-86R01 Summary of contents
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... FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL MB86R01 DATA SHEET July, 2009 the 1.4 edition ...
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... household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i ...
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... Revised figure and table 7.2.2. IDE66 related pin • Revised type • Revised status pin after reset 7.2.3. SD memory controller related pin • Unified SD_DAT[0] and SD_DAT[3:1] 7.2.7. CAN related pin • Revised type FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Revision History Contents ii ...
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... Power On Reset • Revised figure 8-3 • Revised description 8.5.5.1. Clock • Revised table 8-28 8.5.7. I2S Signal Timing • Revised table 8-34 and 8-35 8.5.10. SPI Signal Timing • Revised table 8-38 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Contents iii ...
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... ETM related pin ............................................................................................................................ 24 7.2.21. Power supply related pin ............................................................................................................... 24 7.2.22. MediaLB related pin...................................................................................................................... 25 7.2.23. GPIO related pin ........................................................................................................................... 25 7.2.24. Unused pin .................................................................................................................................... 26 7.2.25. Unused pin with pin multiplex function in the duplex case .......................................................... 34 8. Electrical Characteristics................................................................................. 35 8.1. Maximum Ratings................................................................................................................................. 35 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Contents iv ...
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... Output signal ................................................................................................................. 72 8.5.13. USB2.0 Signal Timing .................................................................................................................. 74 8.5.14. IDE66 Signal Timing .................................................................................................................... 76 8.5.14.1. IDE PIO Timing .................................................................................................................... 76 8.5.14.2. IDE Ultra DMA Timing ........................................................................................................ 78 8.5.15. SD Signal Timing.......................................................................................................................... 80 8.5.15.1. Clock ..................................................................................................................................... 80 8.5.15.2. Input/Output Signal ............................................................................................................... 80 8.5.16. ETM9 Trace Port Signal Timing ................................................................................................... 81 8.5.17. EXIRC Signal Timing ................................................................................................................... 82 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL v ...
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... Outline MB86R01 is LSI product for the graphics applications with ARM Limited's CPU ARM926EJ-S and Fujitsu's GDC MB86296 as its core. This product contains peripheral I/O resources, such as in-vehicle LAN, HDD, and USB; therefore only a single chip of MB86R01 controls main graphics application system which usually requires 2 chips (CPU and GDC ...
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... AHB1: Each bus master of AHB bus such as CPU and DMA controller • HBUS: HOST IF on GDC • DRAW & GEO: Draw (2D/3D drawing) and GEO (geometry engine) on GDC • MBUS: DISP (display controller) and CAP (Video capture) on GDC FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL ETM9CSSingle I-TCM ...
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... A/D converter (ADC) × 2ch APB_TOP_2 This block bridges between APBBRG2 bus and AHB1 bus, and following low-speed peripheral resources are connected. • PWM controller (PWM) • SPI controller (SPI) • CCNT • UART (ch4 and ch5) × 2ch FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 3 ...
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... Built-in 2 channels • Duty ratio and phase are configurable A/D converter • 10 bit successive approximation type A/D converter × 2ch • Sampling rate: 648KS/s (max. sampling plate) • Nonlinearity error: ± 2.0LSB (max.) FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Outline TM processor core 4 ...
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... Number of layer of simultaneous display and number of output display as well as capture input for displaying in high resolution may be restricted due to data supply capacity of graphics memory (DDR2 controller). *2: A part of external pin functions of this LSI is multiplexed. Max. number of usable channel is limited by pin multiplex function setting. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Outline 5 ...
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... MB86R01 DATA SHEET 5. Package dimension Package dimension of MB86R01 is shown below. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 6 ...
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... AE 25 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL (Top view ...
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... VSS VSS XDDMAC XDASP DD[13] DD[9] DD[5] DD[1] K IDE IDE IDE IDE IDE IDE VSS VSS AF XIOCS16 DRESET DD[12] DD[8] DD[4] DD[0] FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL (Top view TRACE MEM XSRST XRST PLLVSS PLLVDD TDO VSS CLK DATA[3] XRD TRACE ...
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... A6 DOUTG0[6] 196 DCLKIN0 197 VSS 198 DCLKO0 199 J3 100 A2 VSS 200 K3 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL PIN NAME Pin NO JEDEC PIN NAME Pin NO JEDEC DE0 201 L3 VIN0[3] 301 GV0 202 M3 VINVSYNC0 302 DOUTB1[5] 203 N3 VINHSYNC0 303 DOUTG1[3] 204 P3 USB_AVSF1 304 ...
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... Mode should be changed when each pin is not in operation. PWM, I2S1, and CAN pins may be duplicated and allocated to external pin depending on group combination; in this case, use either of them. For unused pin, follow the procedure in 1.6.27, unused pin with pin multiplex function in the duplex case. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 10 ...
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... XDACK[6] 108 J2 GV1 DREQ[7] Pin multiplex group #1 mode setting This mode is set with external pin, MPX_MODE_1[1:0]. MPX_MODE_1[1] pin "L" "L" "H" "H" FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Mode 1 Pin related to Pin related to external bus I2S0 interface I2S_ECLK0 I2S_SCK0 I2S_WS0 I2S_SDI0 I2S_SDO0 ...
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... This mode is set with MPX_MODE_2 bit (bit 2-0) in the multiplex mode setting register (CMUX_MD.) MPX_MODE_2 (bit 2-0) of the CMUX_MD register 000 001 010 011 100 101 – 0110 111 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Mode2 Pin related to Pin related Pin related Pin related Pin related Pin related GPIO to CAN ...
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... V1 USB_CRYCK48 230 AD19 USB_PRTPWR Pin multiplex group #3 mode setting This mode is set with external pin, USB_MODE. USB_MODE pin "L" "H" FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Mode 1 Pin related to USB 2.0 function USB_FSDP USB_FSDM USB_HSDP USB_HSDM USB_CRYCK48 USB_PRTPWR Pin multiplex group #3 mode ...
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... IDE_XDDMACK Pin multiplex group #4 mode setting This mode is set with MPX_MODE_4 bit (bit 5-4) in the multiplex mode setting register (CMUX_MD.) MPX_MODE_4 (Bit 5-4) of the CMUX_MD register FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Pin related to Pin related to Pin related to I2S1 CAN GPIO - - - ...
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... C11 TRACEDATA[1] 184 B11 TRACEDATA[0] Pin multiplex group #5 mode setting This mode is set with external pin, MPX_MODE_5[1:0]. MPX_MODE_5[1] pin "L" "L" "H" "H" FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Mode 1 Pin related to Pin related to UART3/4 UART3/4/5 UART_SIN3 UART_SIN3 UART_SOUT3 UART_SOUT3 UART_SIN4 UART_SIN4 ...
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... Pin status after reset Pin status after external pin reset • H: "H" level • L: "L" level • HiZ: High impedance • X: "H" level or "L" level • A: Clock output Description Outline of external pin function FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Status of pin Type after reset 16 Description ...
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... IDE_XDIOW O N IDE_DIORDY I P IDE_DDMARQ I P IDE_XDDMACK O N IDE_CSEL O P IDE_XIOCS16 I N IDE_XDASP I N IDE_DINTRQ I P IDE_XCBLID I N FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Analog Status of pin Type /Digital after reset Chip select Chip select Chip select Read strobe Write strobe MEM_XWR[3] -> MEM_ED[31:24], MEM_XWR[2] -> ...
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... USB_AVDP I - USB_AVDB I - USB_AVSF1 I - USB_AVDF1 I - USB_AVSF2 I - USB_AVDF2 I - 7.2.5. External interrupt controller related pin Pin name I/O Polarity INT_A[3: FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Analog Status of pin Type /Digital after reset Media clock D - HiZ Media command D - HiZ Media data Media write protection Media card detection ...
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... I2S_ECLK1 I - I2S_SCK1 IO - I2S_WS1 IO PN I2S_SDI1 I P I2S_SDO1 O P I2S_ECLK2 I - I2S_SCK2 IO - I2S_WS2 IO PN I2S_SDI2 I P I2S_SDO2 O P FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Analog Status of pin Type /Digital after reset Input data signal Output data signal Clear to send Request to send Input data signal ...
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... I - AD_VRL0 I - AD_AVD I - AD_VR0 O - AD_VIN1 I - AD_VRH1 I - AD_VRL1 I - AD_AVS I - AD_VR1 O - FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Analog Status of pin Type /Digital after reset D POD HiZ I2C clock D POD HiZ I2C data D POD HiZ I2C clock D POD HiZ I2C data Analog Status of pin Type /Digital ...
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... This is process of MDM[3: bit mode. Be sure to open this pin. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Analog Status of pin Type /Digital after reset Address Bank address Data (* HiZ Data mask (* HiZ Data strobe (* HiZ Data strobe (*5) D CLK L Clock output D CLK H Clock output Clock enable D - ...
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... When R:G:B = 5:5:5, lower 1 bit is set with the data contents of the upper 5 bits. [Upper 5 bits] DOUTR0[7:3]=00000 DOUTR0[7:3]=00001-11111 DOUTR1[7:3]=00000 DOUTR1[7:3]=00001-11111 DOUTG0[7:2], DOUTG1[7:2], DOUTB0[7:2], and DOUTB1[7:2] have also the same spec. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Analog Status of pin Type /Digital after reset ...
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... I - 7.2.17. JTAG related pin Pin name I/O Polarity TCK I - XTRST I N TMS I N TDI I - TDO O - FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Analog Status of pin Type /Digital after reset Video capture Data[7: Video capture vertical sync input Video capture horizontal sync input Video input field identification signal 0 in odd ...
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... TRACECLK O - TRACECTL O - TRACEDATA[3: 7.2.21. Power supply related pin Pin name I/O Polarity VSS I - VDDE I - VDDI I - FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Analog Status of pin Type /Digital after reset Return test clock D ST System reset Analog Status of pin Type /Digital after reset JTAG selection ...
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... MediaLB pin of this LSI uses 3.3[V] I/O; therefore, when connecting bus's voltage is not 3.3[V], level conversion at external side is needed. 7.2.23. GPIO related pin Pin name I/O Polarity GPIO_PD[23: *1: GPIO_PD[12:6] is not applicable. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Status of Analog Type pin after /Digital reset D PD HiZ ...
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... AF15 UART_SOUT0 41 AF16 UART_SIN0 42 AF17 UART_SIN1 43 AF18 SD_DAT[0] 44 AF19 SD_WP FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Process Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. Pull up to VDDE or pull down to VSS through high resistance. Connect to VSS. Pull down to VSS through 10kΩ resistance. ...
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... D2 DOUTB1[5], MEM_ED[17], DOUTG0[1] 104 E2 DOUTG1[3], MEM_ED[21], GPIO_PD[7] 105 F2 DOUTG1[7], MEM_ED[25], GPIO_PD[11] FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Process Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. Pull down to VSS through high resistance. Keep the pin open. Pull down to VSS through high resistance. ...
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... AE25 MA[11] 148 AD25 MA[5] 149 AC25 MA[10] 150 AB25 MBA[0] FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Process Pull up to VDDE or pull down to VSS through high resistance. Connect to VDDI. Pull down to VSS through 10kΩ resistance. Connect to VSS. Pull up to VDDE or pull down to VSS through high resistance ...
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... G3 DOUTR1[4], MEM_ED[28], I2S_SDI0 198 H3 DOUTR1[7], MEM_ED[31], I2S_ECLK0 199 J3 VSYNC1, XDACK[6] FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Process Keep the pin open. Pull down to VSS through high resistance. Connect to DDRVDE/2[V]Reference voltage. Pull down to VSS through high resistance. Connect to DDRVDE/2[V]Reference voltage. Pull down to VSS through high resistance. ...
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... W24 MDQ[1] 241 V24 MDQ[7] 242 U24 MDQ[10] 243 T24 MDQ[9] FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Process Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. Connect to VSS. Connect to VDDE. Connect to VSS. Connect to VDDI. Keep the pin open. ...
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... R4 USB_AVSF2 289 T4 USB_AVSF2 292 W4 VIN1[3], RI1[3], CAN_TX1 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Process Pull down to VSS through high resistance. Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. Pull up to VDDE or pull down to VSS through high resistance. ...
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... E23 MEM_ED[6] 334 D23 MEM_ED[10] 335 D22 MEM_EA[5] FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Process Keep the pin open. Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. Pull up to VDDE or pull down to VSS through high resistance. ...
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... AB13 AD_VRL0 379 AB14 AD_VRL1 391 V22 MDQ[6] 398 L22 MDQ[22] FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Process Pull up to VDDE or pull down to VSS through high reistance. Keep the pin open. Connect to VDDE. Pull down to VSS through 10kΩ resistance. Connect to VSS. ...
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... AD4 Pin multiplex group #4:I2S_ECLK1 214 AD3 Pin multiplex group #4:I2S_SCK1 296 AC4 Pin multiplex group #4:I2S_SDO1 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Process Keep the pin open. Pull down to VSS through high resistance. Keep the pin open. Pull down to VSS through high resistance. ...
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... IC and discharges, which may cause circuit destruction. • Applying voltage higher than V higher than the ratings between V current, resulting in thermal destruction of elements. When handling the product, never exceed the maximum ratings. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Rating -0.5 to 1.8 (*1) -0.5 to 4.0 (*2) -0.5 to 2.5 (*3) -0.5 to VDDI + 0.5 (< ...
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... The maximum ratings are the limits that must not be exceeded. As long as USB PHY is used within the range predetermined in the maximum ratings, it never suffers permanent damage. However, this does not assure normal logic operation. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Rating -0.5 to 4.0 -0.5 to VDDE + 0.5 (< ...
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... Using the product without observing the conditions may affect the product's reliability. Performance of this product is not guaranteed using under the unspecified conditions and unspecified combination of logic. Be sure to contact Fujitsu when using the product under such conditions. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Symbol Min ...
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... Set the reset pins (XTRST and XRST) to Low when power-on. Input clock to CLK pin immediately after power-on. It requires at least 100 clocks (input clock to CLK pin) for the reset signal "L" applied to the XRST pin to be transmitted to all internal circuits. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 1 sec. or less 38 ...
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... Keep XRST pin High after setting to Low level for 2μs or more. Access the other registers or memory controller after PLL Lockup Time. When MB86R01 is in DFT mode, XTRST should be input as well as XRST. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Note: Clock is just an image, not the actual one. ...
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... SD_DAT[3:0], TRACECLK, TRACEDATA[3:0], VIN0[7:0], VSYNC0, VSYNC1, XSRST, DE0, DE1, DOUTB0[7:2], DOUTG0[7:2], DOUTR0[7:2], GV0, IDE_CSEL, IDE_DA[2:0], IDE_XDCS[1:0], IDE_XDDMACK, IDE_XDIOR, IDE_XDIOW, IDE_XDRESET, RTCK, SD_CLK, TRACECTL, UART_SOUT[2:0], UART_XRTS0, USB_PRTPWR Driving capability 3: DCLKO[1:0] FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Measurement condition: VDDE = 3.3 ±0.3V, VSS = 0V, T Condition Min. 2.0 -0.3 VDDE - 0 ...
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... MB86R01 DATA SHEET 8.4.1.1. 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 1) Conditions MIN: Process = Slow TYP: Process = Typical T MAX: Process = Fast Figure 8-4 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 1) FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL T = 125°C VDDE = 3 25°C VDDE = 3 ...
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... MB86R01 DATA SHEET 8.4.1.2. 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 2) Conditions MIN: Process = Slow TYP: Process = Typical T MAX: Process = Fast Figure 8-5 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 2) FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL T = 125°C VDDE = 3 25°C VDDE = 3 ...
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... MB86R01 DATA SHEET 8.4.1.3. 3.3V Standard CMOS I/O V-I Characteristics (Driving Capability 3) Conditions MIN: Process = Slow TYP: Process = Typical T MAX: Process = Fast Figure 8-6 3.3 V Standard CMOS I/O V-I Characteristic (Driving Capability 3) FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL T = 125°C VDDE = 3 25°C VDDE = 3 ...
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... Symbol Parameter IOH (DC) Output minimum source DC current IOL (DC) Output minimum sink DC current *1: VDDQ = 1.7V, VOUT = 1420mV *2: VDDQ = 1.7V, VOUT = 280mV *3: The value is different from JESD8-15a. (JESD8-15a: ±13.4mA) FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Min. VREF + 125 -300 Min. VREF + 250 – Condition Min ...
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... AC differential cross point voltage Note: External pin for DDR2SDRAM IO buffer is as follows. MDQSP[3:0], MDQSN[3:0], MDM[3:0], MDQ[31:0], MCKP, MCKN, MA[13:0], MBA[1:0], MCAS, MCKE, MCS, MRAS, MWE, ODTCONT, OCD, ODT, VREF0, VREF1 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Parameter Min. 0.5 × VDDQ - 125 45 Max ...
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... VR is connected to AVS with decoupling capacitor (0.1µF). Unique voltage is supplied to VRH and VRL by voltage source. *2: VZT and VFST are dependent on chip layout and wiring resistance. *3: 1LSB = (VFST-VZT)/1022, INLn = ((1LSBxn + VZT) - Vn)/1LSB, DNLn = ( -Vn)/1LSB - 1 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Value Min. ...
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... C Bus Fast Mode I/O buffer itself has no function to prevent spike of 50ns pulse width (max.). Therefore, provide any input filter to prevent spike for both internal and external semiconductor device. Note: 2 External pin for buffer is as follows. I2C_SCL0, I2C_SDA0, I2C_SCL1, I2C_SDA1 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Standard Mode Symbol Min. Max. VIL -0 ...
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... MB86R01 DATA SHEET 2 8.4.4. V-1 Characteristic Figure FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Voltage (V) 2 Figure 8 V-I Characteristic Figure 48 ...
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... Bus pull-up resistor on upstream port (upstream port receiving) (this is used only in the device mode (HOSTMODE = "0" setting).) Input impedance exclusive of pull-up/pull-down ZINP Termination voltage on upstream port pull-up FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Value Symbol Min. Typ. VHSSQ 100 – ...
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... NOR Flash page Read data hold time dhp t MEM_XRD XRD delay time rdo t MEM_XWR[3:0] XWR delay time wro Standard clock of output delay is internal clock. Standard clock of MEM_RDY is internal clock. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Description Min – – – – – ...
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... MB86R01 DATA SHEET FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Figure 8-8 SRAM/NOR Flash Read Figure 8-9 SRAM/NOR Flash Write 51 ...
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... MB86R01 DATA SHEET Internal CLK t cso MEM_XCS0 MEM_XCS2 MEM_XCS4 t ao MEM_EA[24:1] MEM_RDY MEM_XWR[1: MEM_ED[31:0] FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Figure 8-10 Low speed device Read Min 2Cycle(Internal CLK Min 0[ns] wro t wro Figure 8-11 Low speed device Write 52 t cso wro t ...
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... MB86R01 DATA SHEET FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Figure 8-12 NOR Flash Page Read 53 ...
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... Table 8-22 Write Spec (1 and 2): CK-CMD/ADD and CK-DQS Item CMD/ADD setup valid-data from CK↑ tVD_setup_CMD (tCK/2) - 828 CMD/ADD hold valid-data from CK↑ tVD_hold_CMD Skew between DQS↑ vs. CK↑ *1: Spec for tck = 6ns (333Mbps) is indicated Table 8-23 Write Spec (3): DQ-DQS Item ...
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... MB86R01 DATA SHEET 8.5.2.1. DDR2SDRAM IF Timing Diagram MB86R01 DDR2C * External load condition: PCB design guideline FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL DDR2 SDRAM (DDR2-400) Timing regulation point Figure 8-13 Timing Regulation Point 55 CK CMD/AD DQ DQS ...
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... Figure 8-14 Write Spec (1 and 2): CK-CMD/ADD and CK-DQS DQS_out tVD_setup_DQ DQ_out DM_out FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL tCK = 6ns@166MHz tVD_setup_CMD tSkew_DQS_CK tSkew_DQS_CK tCK = 6ns@166MHz tVD_hold_DQ Valid Data0 Valid Data1 Figure 8-15 Write Spec (3): DQ-DQS 56 tVD_hold_CMD Valid Data Valid Data2 Valid Data3 ...
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... MB86R01 DATA SHEET DQS_in tSETUP_DQ DQ_in DQS_in@delay Min DQS_in@delay Max Figure 8-17 Read Spec (2): DQS-R.T.T (RoundTrip Time) FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL tCK = 6ns@166MHz tHOLD_DQ tHOLD_DQ tSETUP_DQ Figure 8-16 Read Spec (1): DQ-DQS tCK = 6ns@166MHz tRTT_DQS@Min tRTT_DQS@Max 57 ...
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... Data output delay time do GPIO_PD[23:0] t Input data-width dw Internal clock is the standard of output delay. A indicates APB bus clock cycle, and it is different from the output delay standard clock. Internal CLK Output GPIO_PD[23:0] Input FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Description Min. – Figure 8-18 GPIO Timings 58 ...
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... Table 8-27 AC Timing of Ide Data Input Signal Signal Symbol Output delay of PWM_O0 based on APB- PWM_O0 T0 BusClock Output delay of PWM_O1 based on APB- PWM_O1 T1 BusClock APB-BusClock PWM_O0 PWM_O1 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Description T0 T1 Figure 8-19 PWM Output Timing 59 Value Unit Min. Typ. Max. 2.0 – ...
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... Thhsync0 HSYNC Input hold time Twhsync1 HSYNC input pulse width HSYNC1 (i) Tshsync1 HSYNC Input setup time Thhsync1 HSYNC Input hold time VSYNC0 (i) Twvsync0 VSYNC input pulse width VSYNC1 (i) Twvsync1 VSYNC input pulse width FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Description Min. – – – ...
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... Tdcsync1 CSYNC output delay time GV0 Tdgv0 GV output delay time GV1 Tdgv1 GV output delay time Note: If hold time is deficient, inverting DCLKO clock is recommended. n DCLK I 1/Fdclki n HSYNC (i) n VSYNC (i) FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Description Min Thdclki Tldclki n Twhsync n n Tshsync Thhsync n Twvsync ...
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... DCLKO 1/Fdclko n DCLKO (inverted) n DOUTR [5:0] n DOUTG [5:0] n DOUTB [5:0] n HSYNC (o) n VSYNC (o) n CSYNC n GV Figure 8-21 Display Output Signal Timing There is no definition of AC characteristics about analog signal. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL n n Tddrgb n Tdhsync n Tdvsync n Tdcsync n Tdgv 62 ...
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... VINVSYNC1 t Input hold Time HVSI t Input setup time VINFID0, SFI VINFID1 t Input hold Time HFI CCLK0, CCLK1 Figure 8-22 Video Capture Clock Input Signal Timing FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Description Description 1/f CCLK t t HCCLK LCCLK 63 Value Unit Min. Typ. ...
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... MB86R01 DATA SHEET CCLK0/1 VIN0 /1 RI,GI,BI VINHSYNC0/1 VINVSYNC0/1 VINFID0/1 Figure 8-23 Video Capture Input Signal Timing FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL t t SVI HVI t t SRI HRI t t SGI HGI t t SBI HBI t t SHSI HHSI t t SVSI HVSI t t SFI ...
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... Delay time, I2S_SCKx high to the first bit of a transmit t frame when FSPH bit of I2Sx_CNTREG register is 1. dfb1 (master mode) B indicates AHB bus clock frequency. T indicates I2S_SCKx cycle. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Description Min. – 0.45*T 0.45*T 8 ...
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... FSLN is bit 1 of I2Sx_CNTREG register. t scyc t t shw I2S_SCKx t t sfi hfi I2S_WSx (FSPH=0, FSLN=0) I2S_WSx (FSPH=1,FSLN=0) t sfi I2S_WSx (FSPH=0, FSLN=1) I2S_WSx (FSPH=1, FSLN=1) I2S_SDOx I2S_SDIx FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL mlw t dfs t t dfs dfs t dfs t t dfb1 ddo sdi sdi ...
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... A indicates APB bus clock cycle, and it is different from the output delay standard clock. Internal CLK UART_SOUT0 UART_SOUT1 UART_SOUT2 UART_SOUT3 UART_SOUT4 UART_SOUT5 UART_XRTS0 UART_SIN0 UART_SIN1 UART_SIN2 UART_SIN3 UART_SIN4 UART_SIN5 UART_XCTS0 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Description Min. – 16*A – rtso t dw ～ ～ ...
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... PCLK = APB bus clock cycle STOP I2C_SDA0(in) I2C_SDA1(in) T S2SCLI I2C_SCL0(in) I2C_SCL1(in) T WBFI STOP I2C_SDA0(out) I2C_SDA1(out) T S2SCLO I2C_SCL0(out) I2C_SCL1(out) FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Description Min. Normal mode 250 (*1) High-speed mode 100 (*1) Normal mode 0.0 (*1) High-speed mode 0.0 (*1) Normal mode 4.7 (*1) High-speed mode 1.3 (*1) Normal mode 1 ...
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... Hold time, SPI_DI valid after SPI_SCK hdi t SPI_DO Delay time, SPI_SCK do t SPI_SS Delay time, SPI_SCK sso A indicates APB bus clock frequency. SPI_SCK SPI_SCK SPI_DO SPI_DI SPI_SS Polarity of SPI_SCK is determined by the register setting. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Description Min. – cyc sdi hdi ...
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... CAN_TX0 t Data output delay time do CAN_TX1 CAN_RX0 t Input data width dw CAN_RX1 Internal clock is the standard of output delay. Internal CLK CAN_TX0 CAN_TX1 CAN_RX0 CAN_RX1 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Description Min. – 1000 ～ ～ Figure 8-29 CAN Timing 70 Value Unit Typ. ...
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... The board must be designed to ensure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Value Description Min ...
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... The board must be designed to ensure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Value Description Min ...
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... MB86R01 DATA SHEET Figure 8-31 MediaLB Pulse Width Variation Timing FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Figure 8-30 MediaLB Timing 73 ...
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... USB_HSDP t Rise time (10% - 90%) USB_HSDM lr USB_FSDP t Fall time (10% - 90%) lf USB_FSDM t Rise and fall time matching lrfm FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Description Min. 500 500 Complying with USB2.0 specification (section 7.1.2) 40.5 479.760 Complying with USB2.0 specification (section 7.1.2) Description Min. ...
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... MB86R01 DATA SHEET Differential Data Lines Figure 8-32 Data Signal Rise and Fall Time FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 90% 10% Rise Time 75 90% 10% Fall Time ...
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... IDE_XDIOR/IDE_XDIOW to address valid t9 hold (min.) Read data valid to IDE_DIORDY active (if tRD IDE_DIORDY initially low after tA) (min.) tA IDE_DIORDY setup time tB IDE_DIORDY pulse width (max.) tC IDE_DIORDY assertion to release (max.) FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Value mode0 mode1 mode2 mode3 600 383 330 180 70 ...
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... MB86R01 DATA SHEET IDE_XDCS[1:0] IDE_DA[2:0] IDE_XDIOR/ IDE_XDIOW IDE_DD[15:0] (Write Data) IDE_DD[15:0] (Read Data) IDE_DIORDY (no wait) IDE_DIORDY (wait) FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL t0 Valid tRD tB Figure 8-33 PIO Access Timing 77 t9 t2i DATA t3 t4 DATA t5 t6 t6Z tC ...
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... Setup and hold times for DMACK- Tack (before assertion or negation) Time from STROBE edge to Tss negation of DMARQ or assertion of STOP (when sender terminates burst) FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Value mode0 mode1 mode2 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. ...
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... Tui IDE_XDDMACK Tack Tenv Tli IDE_XDIOW (STOP) Tziordy IDE_DIORDY (DDMARDY) IDE_XDIOR (HSTROBE) IDE_DD[15:0] IDE_XDCS[1:0] Tack IDE_DA[2:0] FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Tcycle DATA DATA DATA Tdvs Tdvh Tdvs Tdvh Figure 8-34 IDE Read Access Timing Tui Trfs Tcycle Tcycle T2cycle DATA ...
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... SD_DAT[3:0] tS_DAT edge) Input data hold (standard of SD_CLK rising tH_DAT edge) SD_CLK SD_DAT[3:0] tD_DAT SD_CLK SD_DAT[3:0] tS_DAT FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Description Description t_SDCLK Figure 8-36 Output Timing to Media VALID DATA tH _DAT Figure 8-37 Input Timing from Media 80 Value Unit Min ...
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... TRACEDATA setup time to rising edge of TRACECLK. Tdatahr TRACEDATA hold time to rising edge of TRACECLK. TRACEDATA[3:0] Tdatasf TRACEDATA setup time to falling edge of TRACECLK. Tdatahf TRACEDATA hold time to falling edge of TRACECLK. TRACECLK TRACECTL TRACEDATA[3:0] FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Description Tctlsf Tctlhf Tctlsr Tctlhr Tdatasf Tdatahf Tdatasr Tdatahr [NOTE] MB86R01 supports only half-rate clocking mode ...
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... The case that external interrupt input request is edge (rising edge and falling edge), input data width (tdw) is regulated as follows. When level ("H" or "L") is selected as the request, it should be held until interrupt process is completed. A indicates APB bus clock cycle. APB BUS CLK INT_A[3:0] FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL Description Min. A ...
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