SK-86R01 Fujitsu, SK-86R01 Datasheet - Page 10

• Manufacturer Part Number: SK-86R01
• Description: KIT, STARTER, JADE, MB86R01
• Manufacturer: Fujitsu
• Type: Evaluation Boardr

Specifications of SK-86R01

• Kit Contents: A Base Board, A Graphics Subboard, A Video Extension Input Board, A Video Extension Output Board
• Mcu Supported Families: MB86R01
• Silicon Manufacturer: Fujitsu
• Core Architecture: ARM
• Core Sub-architecture: ARM926EJ-S
• Features: Built-in SRAM, Remap/Boot Control Function
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FUJITSU MICROELECTRONICS
PROPRIETARY AND CONFIDENTIAL
MB86R01 DATA SHEET
4.
Function list of MB86R01 is shown below.
CPU core
Bus architecture
Interrupt
Clock
Reset
Remap
External bus interface
DDR2 controller
Built-in SRAM
DMAC
Timer
GPIO (*2)
PWM (*2)
A/D converter
Function list
Function
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ARM926EJ-S
Core operation frequency: 333MHz
16KB instruction cache
16KB data cache
Tightly-Coupled memory for 16KB instruction (ITCM)
Tightly-Coupled memory for 16KB data (DTCM)
ETM9CS Single and JTAG ICE debugging interface
Java acceleration (Jazelle technology)
Multilayer AHB bus architecture (software interrupt)
Speeding up data transfer between main memory and each bus master with 64 bit AXI
bus
High-speed interrupt × 1ch h (soft interrupt)
Normal interrupt × 64ch (external interrupt × 4ch + built-in internal interrupt × 60ch)
Up to 16 interrupt levels are settable by channel
PLL multiplication: selectable from ×15 ~ 49
Operation frequency: 333MHz (CPU), 83MHz (AHB), 41.5MHz (APB)
Low power consumption mode (clock to ARM and module is stoppable)
Hardware reset, software reset, and watchdog reset
ROM area is able to be mapping to built-in SRAM area
Three chip select signals
Provided 32M byte address space in each chip select
Supported 16/32 bit width SRAM/Flash ROM connection
Programmable weight controller
Encrypted ROM compound engine
Supported DDR2SDRAM (DDR2-400)
Connectable capacity: 256 ~ 512M bit × 2 or 256 ~ 512M bit × 1
I/O width: Selectable from ×16/×32 bit
Max. transfer rate: 166MHz/333Mbps
Mounted general purpose SRAM of 32KB × 2 (32 bit bus)
AHB connection × 8ch
Transfer mode: Block, burst, and demand
32/16 bit programmable × 2 channels
Max. 24 is usable
Interrupt function
Built-in 2 channels
Duty ratio and phase are configurable
10 bit successive approximation type A/D converter × 2ch
Sampling rate: 648KS/s (max. sampling plate)
Nonlinearity error: ± 2.0LSB (max.)
TM
processor core
4
Outline