SK-86R01 Fujitsu, SK-86R01 Datasheet - Page 11

• Manufacturer Part Number: SK-86R01
• Description: KIT, STARTER, JADE, MB86R01
• Manufacturer: Fujitsu
• Type: Evaluation Boardr

Specifications of SK-86R01

• Kit Contents: A Base Board, A Graphics Subboard, A Video Extension Input Board, A Video Extension Output Board
• Mcu Supported Families: MB86R01
• Silicon Manufacturer: Fujitsu
• Core Architecture: ARM
• Core Sub-architecture: ARM926EJ-S
• Features: Built-in SRAM, Remap/Boot Control Function
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MB86R01 DATA SHEET
FUJITSU MICROELECTRONICS
PROPRIETARY AND CONFIDENTIAL
GDC (*1)
I2S (*2)
UART (*2)
I
SPI (*2)
CAN (*2)
MediaLB (*2)
USB (*2)
IDE (*2)
SDMC
CCNT
JTAG
*1: Number of layer of simultaneous display and number of output display as well as capture input for displaying
*2: A part of external pin functions of this LSI is multiplexed. Max. number of usable channel is limited by pin
2
C
in high resolution may be restricted due to data supply capacity of graphics memory (DDR2 controller).
multiplex function setting.
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Architecture)
BT.601, BT.656, and RGB666
Max. 2 inputs
Display controller
RGB666 or RGB888 output
Max. resolution is 1024 × 768
Max. 6 layered display
Max. 2 screen output
Digital video capture function
Geometry engine (MB86296 compatible display list is usable)
2D/3D drawing function (MB86296 compatible display list is usable)
Audio output × 3ch (L/R)/Audio input × 3ch (L/R)
Supported three-wire serial (I2S, MSB-Justified) and serial PCM data transfer interface
Master/Slave operations are selectable
Resolution capability: Max. 32 bit/sample
Max. 6 channels (dedicated channel: 3ch, option: 3ch)
1 channel: capable of input/output CTS/RTS signals
8 bit pre-scaler for baud rate clock generation
Enabled DMA transfer
3.3V pin × 2ch
Supported standard mode (max. 100kbps)/high-speed mode (max. 400kbps)
Full duplex/Synchronous transmission
Transfer data length: 1 bit unit (max. 32 bit) (programmable setting)
Mounted BOSCH C_CAN module × 2ch
Conformed to CAN protocol version 2.0 part A and B
I/O voltage: 3.3V
16 channels
MediaLB clock speed: 256Fs/512Fs/1024Fs
Built-in 9K bit channel buffer
USB 2.0 compliant Host/Function controller × 1ch (pin multiplex)
HS/FS protocol support
Supported ATA/ATAPI-5
Equipped 1 channel
Supported primary IDE channel
Equipped transmission FIFO buffer (512 byte × 2) and reception FIFO buffer (512 byte
× 2) for the ultra DMA transfer
Unsupported single word DMA and multiword DMA
Conformed to SD memory card physical layer specification 1.0
Equipped 1 channel
Supported SD memory card and multimedia card
Unsupported SPI mode, SDIO mode, and CPRM
Mode selection of multiplex pin group 2 and 4
Software reset control
AXI interconnection control (priority and WAIT setting)
Conformed to IEIEEE1149.1 (IEEE Standard Test Access Port and Boundary-Scan
Supported JTAG ICE connection
(supported VBus and isochronous transfer)
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Outline