SK-86R01 Fujitsu, SK-86R01 Datasheet - Page 66

• Manufacturer Part Number: SK-86R01
• Description: KIT, STARTER, JADE, MB86R01
• Manufacturer: Fujitsu
• Type: Evaluation Boardr

Specifications of SK-86R01

• Kit Contents: A Base Board, A Graphics Subboard, A Video Extension Input Board, A Video Extension Output Board
• Mcu Supported Families: MB86R01
• Silicon Manufacturer: Fujitsu
• Core Architecture: ARM
• Core Sub-architecture: ARM926EJ-S
• Features: Built-in SRAM, Remap/Boot Control Function
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FUJITSU MICROELECTRONICS
PROPRIETARY AND CONFIDENTIAL
MB86R01 DATA SHEET
8.5.5.
8.5.5.1.
8.5.5.2.
Table 8-28 AC timing of Video Interface Clock Signal
DCLKI0
DCLKI1
DCLK (internal) Tldclk0
DCLK (internal) Tldclk1
DCLKO0
DCLKO1
*1: Internal display clock of PLL synchronization mode is generated by division of internal PLL in the display clock
*2: DCLKI or internal display clock of PLL is output.
1) Applied the signal only in PLL synchronization mode (CKS = 0)
Table 8-29 AC Timing of Video Interface Input Signal (1)
HSYNC0 (i)
HSYNC1 (i)
VSYNC0 (i)
VSYNC1 (i)
2) Applied the signal only in DCLKI synchronization mode (CKS = 1)
Table 8-30 AC Timing of Video Interface Input Signal (2)
HSYNC0 (i)
HSYNC1 (i)
VSYNC0 (i)
VSYNC1 (i)
(Reference clock = Clock output from internal PLL)
(Reference clock = DCLKI)
prescaler.
Signal
Signal
Signal
GDC Display Signal Timing
Clock
Input Signal
Fdclki0
Thdclki0
Tldclki0
Fdclki1
Thdclki1
Tldclki1
Fdclko
Fdclko
Twhsync0 HSYNC input pulse width
Twvsync1 VSYNC input pulse width
Twvsync
Twvsync
Twhsync0 HSYNC input pulse width
Tshsync0 HSYNC Input setup time
Thhsync0 HSYNC Input hold time
Twhsync1 HSYNC input pulse width
Tshsync1 HSYNC Input setup time
Thhsync1 HSYNC Input hold time
Twvsync0 VSYNC input pulse width
Twvsync1 VSYNC input pulse width
Symbol
Symbol
Symbol
DCLKI frequency
DCLKI H width
DCLKI L width
DCLKI frequency
DCLKI H width
DCLKI L width
DCLK frequency (*1)
DCLK frequency (*1)
DCLKO frequency
DCLKO frequency
VSYNC input pulse width
VSYNC input pulse width
Description
Description
Description
60
Min.
Min.
Min.
3.0
3.0
3.0
6.0
1.0
3.0
6.0
1.0
–
5
5
–
5
5
–
–
–
–
1
1
1
1
Value
Value
Typ.
Typ.
Value
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max.
Max.
Max.
80
80
80
80
80
80
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
HSYNC
HSYNC
HSYNC
HSYNC
Clock
Clock
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
Clock
Clock
Unit
ns
ns
ns
ns
ns
ns
ns
ns