SK-86R01 Fujitsu, SK-86R01 Datasheet - Page 29

• Manufacturer Part Number: SK-86R01
• Description: KIT, STARTER, JADE, MB86R01
• Manufacturer: Fujitsu
• Type: Evaluation Boardr

Specifications of SK-86R01

• Kit Contents: A Base Board, A Graphics Subboard, A Video Extension Input Board, A Video Extension Output Board
• Mcu Supported Families: MB86R01
• Silicon Manufacturer: Fujitsu
• Core Architecture: ARM
• Core Sub-architecture: ARM926EJ-S
• Features: Built-in SRAM, Remap/Boot Control Function
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MB86R01 DATA SHEET
FUJITSU MICROELECTRONICS
PROPRIETARY AND CONFIDENTIAL
7.2.15.
7.2.16.
7.2.17.
VIN0[7:0]
VINVSYNC0
VINHSYNC0
VINFID0
CCLK0
VIN1[7:0]
VINVSYNC1
VINHSYNC1
VINFID1
CCLK1
RI1[7:2]
GI1[7:2]
BI1[7:2]
*1: GI1[3] is not applicable.
*2: BI1[2] is not applicable.
CLK
XRST
CRIPM[3:0]
VINITHI
PLLBYPASS
BIGEND
PLLVSS
PLLTDTRST
PLLVDD
TCK
XTRST
TMS
TDI
TDO
Pin name
Pin name
Pin name
Video capture related pin
System related pin
JTAG related pin
I/O
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Polarity
Polarity
Polarity
N
N
N
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
/Digital
/Digital
/Digital
Analog
Analog
Analog
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
D
A
D
PD (*1)
PD (*2)
ST, PU
ST, PU
Type
CLK
CLK
Type
CLK
Type
PD
PD
PD
PD
PD
PU
PU
ST
Tri
-
-
-
-
-
-
-
-
-
-
-
23
Status of pin
Status of pin
Status of pin
after reset
after reset
after reset
HiZ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
field
field
Input clock
System reset
PLLMODE setting
Boot high address
PLL bypass mode setting
LSI endian setting
Low: Little endian
High: Big endian
PLL ground
Test pin
Pull up the pin to VDDE, via high resistance
PLL power supply
Test clock
Test reset
Test mode
Test data input
Test data output
Video capture Data[7:0]
Video capture vertical sync input
Video capture horizontal sync input
Video input field identification signal 0 in odd
Video capture input clock
Video capture Data[7:0]
Video capture vertical sync input
Video capture horizontal sync input
Video input field identification signal 0 in odd
Video capture input clock
NRGB666 capture DataR[7:2] (optional)
NRGB666 capture DataG[7:2] (optional)
NRGB666 capture DataB[7:2] (optional)
Description
Description
Description