SK-86R01 Fujitsu, SK-86R01 Datasheet - Page 84

• Manufacturer Part Number: SK-86R01
• Description: KIT, STARTER, JADE, MB86R01
• Manufacturer: Fujitsu
• Type: Evaluation Boardr

Specifications of SK-86R01

• Kit Contents: A Base Board, A Graphics Subboard, A Video Extension Input Board, A Video Extension Output Board
• Mcu Supported Families: MB86R01
• Silicon Manufacturer: Fujitsu
• Core Architecture: ARM
• Core Sub-architecture: ARM926EJ-S
• Features: Built-in SRAM, Remap/Boot Control Function
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FUJITSU MICROELECTRONICS
PROPRIETARY AND CONFIDENTIAL
MB86R01 DATA SHEET
8.5.14.2.
T2cycleTYP
T2cycle
Tcycle
Tdvs
Tdvh
Tfs
Tli
Tmli
Tui
Taz
Tzah
Tzad
Tenv
Trfs
Trp
Tiordyz
tziordy
Tack
Tss
Symbol
Table 8-51 AC timing of Ultra DMA
Typical sustained average 2 cycle
time
2 cycle time allowing for clock
variations (from rising edge to next
rising edge or from falling edge to
next falling edge of STROBE)
Cycle time allowing for asymmetry
and clock variations (from STROBE
edge to STROBE edge)
Data valid setup time at sender (from
data valid until STROBE edge)
Data valid setup time at sender (from
STROBE edge until data may
become invalid)
First STROBE time (for device to
first negateDSTROBE from STOP
during data in Burst)
Limited interlock time
Interlock time with minimum
Unlimited interlock time
Maximum time allowed for output
drivers to release (from asserted or
negated)
Minimum delay time required for
output
Drivers to assert or negate (from
released)
Envelope time (from DMACK- to
STOP and HDMARDY- during data
in burst initiation and from
IDE_XDDDMACK to STOP during
data out burst initiation)
Ready-to-final-STROBE time (no
STROBE edges shall be sent this
long after negation of DMARDY)
Minimum time to assert STOP or
negate IDE_DMARQ
Maximum time before releasing
IDE_DIORDY
Minimum time before driving
STROBE
Setup and hold times for DMACK-
(before assertion or negation)
Time from STROBE edge to
negation of DMARQ or assertion of
STOP (when sender terminates burst)
IDE Ultra DMA Timing
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
240
230
112
160
6.2
70
20
20
20
20
50
–
0
0
–
0
–
–
0
mode0
78
230
150
70
10
75
20
–
–
–
–
–
–
–
–
–
–
–
–
–
160
154
125
6.2
73
48
20
20
20
20
50
–
0
0
–
0
–
–
0
mode1
200
150
10
70
70
20
–
–
–
–
–
–
–
–
–
–
–
–
–
120
115
100
6.2
54
30
20
20
20
20
50
–
0
0
–
0
–
–
0
mode2
Value
150
170
10
70
60
20
–
–
–
–
–
–
–
–
–
–
–
–
–
100
6.2
90
86
39
20
20
20
20
20
50
–
0
0
–
0
–
–
0
mode3
130
100
10
55
60
20
–
–
–
–
–
–
–
–
–
–
–
–
–
100
6.2
6.7
60
57
25
20
20
20
20
50
–
0
0
–
0
–
–
0
mode4
120
100
10
55
60
20
–
–
–
–
–
–
–
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns