SK-86R01 Fujitsu, SK-86R01 Datasheet - Page 18

• Manufacturer Part Number: SK-86R01
• Description: KIT, STARTER, JADE, MB86R01
• Manufacturer: Fujitsu
• Type: Evaluation Boardr

Specifications of SK-86R01

• Kit Contents: A Base Board, A Graphics Subboard, A Video Extension Input Board, A Video Extension Output Board
• Mcu Supported Families: MB86R01
• Silicon Manufacturer: Fujitsu
• Core Architecture: ARM
• Core Sub-architecture: ARM926EJ-S
• Features: Built-in SRAM, Remap/Boot Control Function
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

24
Pin No. JEDEC
208
118
209
292
119
210
293
211 AA3
294 AA4
202
203
112
123 AD2
122 AC2
121 AB2
295 AB4
212 AB3
19
22
23
FUJITSU MICROELECTRONICS
PROPRIETARY AND CONFIDENTIAL
MB86R01 DATA SHEET
Pin multiplex group #2 (setting register: PIN MPX Select.MPX_MODE_2 [2:0])
AD1 -
AB1
AC1
W1
W2
W3
W4
M3
V3
Y2
Y3
Y4
N3
N2
Pin multiplex group #2 mode setting
Pin related to
VINVSYNC1
VINHSYNC1
VINVSYNC0
VINHSYNC0
VINFID1
VINFID0
CAP0/1
VIN1[7]
VIN1[6]
VIN1[5]
VIN1[4]
VIN1[3]
VIN1[2]
VIN1[1]
VIN1[0]
This mode is set with MPX_MODE_2 bit (bit 2-0) in the multiplex mode setting register
(CMUX_MD.)
MPX_MODE_2 (bit 2-0) of
-
-
-
-
-
-
the CMUX_MD register
-
Mode0
Pin related
PWM_O0
PWM_O1
to PWM
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
101 – 0110
I2S_ECLK2 BI1[5]
Pin related
I2S_SDO2
I2S_SCK2
I2S_SDI2
000
001
010
011
100
I2S_WS2
111
to I2S2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin related to
VINVSYNC1
VINHSYNC1
(NRGB666)
VINFID1
Mode1
RI1[7]
RI1[6]
RI1[5]
RI1[4]
RI1[3]
RI1[2]
GI1[7]
GI1[6]
GI1[5]
GI1[4]
GI1[3]
GI1[2]
BI1[7]
BI1[6]
BI1[4]
BI1[3]
BI1[2]
CAP1
Pin related to
-
GPIO_PD[5]
GPIO_PD[4]
GPIO_PD[3]
GPIO_PD[2]
GPIO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin related
CAN_TX0
CAN_RX0
CAN_TX1
CAN_RX1
to CAN
Pin multiplex group #2 mode
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Mode2
I2S_ECLK2 -
I2S_ECLK1
Pin related
I2S_SCK1
I2S_SDO1
I2S_SDO2
I2S_SCK2
I2S_SDI2
to I2S1/2
I2S_WS1
I2S_SDI1
I2S_WS2
(Initial value)
-
-
-
-
-
-
-
-
-
-
-
Reserved
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
MLB_DATA
to MediaLB
Pin related
MLB_CLK
12
MLB_SIG
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GPIO_PD[3]
GPIO_PD[2]
GPIO_PD[5]
GPIO_PD[4]
Pin related
to GPIO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin related
CAN_TX0
CAN_RX0
CAN_TX1
CAN_RX1
to CAN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I2S_ECLK1
Pin related
I2S_SCK1
I2S_SDO1
Mode3
I2S_WS1
I2S_SDI1
to I2S1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
to MediaLB
MLB_DATA
Pin related
MLB_CLK
MLB_SIG
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Reserved
(Input/Outpu
related to
SPI_SCK
SPI_DO GPIO_PD[1]
SPI_SS
SPI_DI
Pin
SPI
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
t)
GPIO_PD[0] -
GPIO_PD[5]
GPIO_PD[4]
GPIO_PD[3]
GPIO_PD[2]
Pin related
to GPIO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin related
CAN_RX0
CAN_RX1
CAN_TX0
CAN_TX1
to CAN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Mode4
-
I2S_ECLK1
Pin related
I2S_SCK1
I2S_SDO1
I2S_SCK2
to I2S1/2
I2S_WS1
I2S_SDI1
I2S_WS2
I2S_SDI2
-
-
-
-
-
-
-
-
-
-
-
-
Pin related to
-
MLB_DATA
MLB_CLK
MLB_SIG
MediaLB
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-