IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 183

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 6: Signals
Frame Reader
Table 6–13. Frame Buffer Signals (Part 3 of 3)
Frame Reader
Table 6–14. Frame Reader Signals (Part 1 of 2)
May 2011 Altera Corporation
write_master_av_clock
write_master_av_reset
write_master_av_waitrequest
write_master_av_write
write_master_av_writedata
writer_control_av_chipselect
writer_control_av_readdata
writer_control_av_write
writer_control_av_writedata
Notes to
(1) Additional clock and reset signals are available when you turn on Use separate clocks for the Avalon-MM master interfaces.
(2) These ports are present only if the control interface for the reader component has been enabled.
(3) These ports are present only if the control interface for the writer component has been enabled
clock
reset
dout_data
dout_endofpacket
dout_ready
Table
6–13:
Signal
Signal
Table 6–14
function.
shows the input and output signals for the Frame Reader MegaCore
Direction
In
In
In
Out
Out
In
Out
In
In
Direction
In
In
Out
Out
In
write_master port clock signal. The interface operates on the
rising edge of the clock signal.
write_master port reset signal. The interface resets
asynchronously when you assert this signal. You must deassert
this signal synchronously to the rising edge of the clock signal.
write_master port Avalon-MM waitrequest signal. The
system interconnect fabric asserts this signal to cause the master
port to wait.
write_master port Avalon-MM write signal. Asserted to
indicate write requests from the master to the system interconnect
fabric.
write_master port Avalon-MM writedata bus. These output
lines carry data for write transfers.
writer_control slave port Avalon-MM chipselect signal. The
writer_control port ignores all other signals unless you assert
this signal.
writer_control slave port Avalon-MM readdata bus. These
output lines are used for read transfers.
writer_control slave port Avalon-MM write signal. When you
assert this signal, the writer_control port accepts new data
from the writedata bus.
writer_control slave port Avalon-MM writedata bus. These
input lines are used for write transfers.
The main system clock. The MegaCore function operates on the
rising edge of the clock signal.
The MegaCore function asynchronously resets when you assert
reset. You must deassert reset synchronously to the rising
edge of the clock signal.
dout port Avalon-ST data bus. This bus enables the
transfer of pixel data out of the MegaCore function.
dout port Avalon-ST endofpacket signal. This signal
marks the end of an Avalon-ST packet.
dout port Avalon-ST ready signal. The downstream
device asserts this signal when it is able to receive data.
(3)
Description
(3)
Description
Video and Image Processing Suite User Guide
(1)
(3)
(3)
(1)
6–19