IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 21

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 1: About This MegaCore Function Suite
Performance and Resource Utilization
Table 1–12. Color Space Converter Performance (Part 2 of 2)
Table 1–13. Control Synchronizer Performance
Table 1–14. Deinterlacer Performance (Part 1 of 2)
May 2011 Altera Corporation
Notes to
(1) EP4CGX22BF14C6 devices.
(2) 5SGXEA7H3F35C3 devices.
Synchronizing the configuration of other MegaCore functions with 2 channels in parallel, and the maximum number of
control data entries that can be written to other cores is 3.
Synchronizing the configuration of other MegaCore functions with 3 channels in parallel, and the maximum number of
control data entries that can be written to other cores is 3.
Synchronizing the configuration of other MegaCore functions with 3 channels in parallel, and the maximum number of
control data entries that can be written to other cores is 10.
control data entries that can be written to other cores is 3.
Notes to
(1) EP4CGX15BF14C6 devices.
(2) 5SGXEA7H3F35C3 devices.
Deinterlacing 64×64 pixel 8-bit R’G’B’ frames using the bob algorithm with scanline duplication.
Synchronizing the configuration of other MegaCore functions with 3 channels in sequence, and the maximum number of
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Device Family
Device Family
Device Family
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Table
Table
Control Synchronizer
Deinterlacer
(2)
(2)
(2)
(2)
(2)
1–12:
1–23:
(1)
(1)
(1)
(1)
(1)
Combinational
Combinational
Table 1–13
Table 1–14
LUTs/ALUTs
LUTs/ALUTs
Combinational
1,256
LUTs/ALUTs
259
609
408
624
418
697
594
398
525
shows the performance figures for the Control Synchronizer.
shows the performance figures for the Deinterlacer.
Registers
Registers
Logic
Logic
1,582
1,052
359
805
574
839
604
750
398
Registers
Logic
582
Bits
Bits
—
—
—
—
—
—
—
—
—
17,280
Bits
Memory
Memory
M9K
—
M9K
—
—
—
—
0
0
0
0
Memory
M9K
4
M20K
M20K
0
—
—
—
—
0
0
0
0
M20K
Video and Image Processing Suite User Guide
—
(9×9)
—
(9×9)
DSP Blocks
—
—
—
—
—
—
—
—
DSP Blocks
(9×9)
—
DSP Blocks
(18×18)
(18×18)
(18×18)
3
—
—
—
—
—
—
—
—
—
209.69
380.37
212.27
378.79
211.77
364.03
212.18
377.93
(MHz)
204.83
(MHz)
f
(MHz)
400
f
MAX
f
MAX
MAX
1–13