IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 22

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

1–14
Table 1–14. Deinterlacer Performance (Part 2 of 2)
Table 1–15. Deinterlacer II Performance
Table 1–16. Frame Buffer Performance (Part 1 of 2)
Video and Image Processing Suite User Guide
Deinterlacing with scanline interpolation using the bob algorithm working on 352×288 pixel 12-bit Y’CbCr 4:2:2 frames.
Deinterlacing PAL (720×576) with 8-bit Y'CbCr 4:4:4 color using the motion-adaptive algorithm.
Deinterlacing HDTV 1080i resolution with 12-bit Y’CbCr 4:4:4 color using the weave algorithm.
Notes to
(1) EP4CGX15BF14C6 devices.
(2) 5SGXEA7H3F35C3 devices.
Deinterlacing PAL (720×576) with 8-bit Y'CbCr 4:4:4 color using the motion-adaptive algorithm.
Deinterlacing PAL (720×576) with 8-bit Y'CbCr 4:4:4 color using the motion-adaptive high quality algorithm.
Notes to
(1) EP4CGX22CF19C6 devices.
(2) 5SGXEA7H3F35C3 devices.
Double-buffering XGA (1024×768) 8-bit RGB with a sequential data interface.
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Device Family
Device Family
Device Family
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Table
Table
Deinterlacer II
Frame Buffer
1–14:
1–15:
(2)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
Combinational
Table 1–15
Table 1–16
LUTs/ALUTs
Combinational
Combinational
LUTs/ALUTs
LUTs/ALUTs
1,489
10,766
6,992
5,188
2,790
2,144
4,990
3,696
8,252
389
632
454
shows the performance figures for the Deinterlacer II.
shows the performance figures for the Frame Buffer.
Registers
Logic
1,942
Registers
Registers
9,697
7,879
3,313
2,299
4,821
4,036
7,869
7,010
Logic
Logic
332
704
398
7,936
Bits
157,372
157,372
48,398
48,244
50,356
50,594
17,280
14,400
14,400
2,566
2,566
Bits
Bits
Memory
M9K
Memory
4
Memory
M9K
M9K
72
—
83
—
—
—
37
—
14
—
3
M20K
—
Chapter 1: About This MegaCore Function Suite
M20K
—
59
—
70
M20K
—
—
24
—
14
2
1
(9×9)
Performance and Resource Utilization
—
(9×9)
DSP Blocks
—
—
(9×9)
4
8
DSP Blocks
—
—
—
—
—
—
DSP Blocks
4
May 2011 Altera Corporation
(18×18)
(18×18)
(18×18)
—
—
—
2
4
—
—
—
—
—
—
2
153.23
203.46
153.59
203.67
175.59
294.55
202.18
303.58
135.15
219.68
176.03
283.61
(MHz)
(MHz)
(MHz)
f
f
f
MAX
MAX
MAX