IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 186

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

6–22
Interlacer
Table 6–16. Interlacer Signals
Video and Image Processing Suite User Guide
clock
reset
control_av_address
control_av_chipselect
control_av_readdata
control_av_waitrequest
control_av_write
control_av_writedata
din_data
din_endofpacket
din_ready
din_startofpacket
din_valid
dout_data
dout_endofpacket
dout_ready
dout_startofpacket
dout_valid
Note to
(1) These ports are present only if you turn on Pass-through mode.
Table 6–5
Signal
Table 6–5
shows the input and output signals for the Interlacer MegaCore function.
Direction
In
In
In
In
Out
Out
In
In
In
In
Out
In
In
Out
Out
In
Out
Out
The main system clock. The MegaCore function operates on the rising edge
of the clock signal.
The MegaCore function asynchronously resets when you assert reset. You
must deassert reset synchronously to the rising edge of the clock signal.
control slave port Avalon-MM address bus. Specifies a word offset into
the slave address space.
control slave port Avalon-MM chipselect signal. The control port
ignores all other signals unless you assert this signal.
control slave port Avalon-MM readdata bus. These output lines are used
for read transfers.
control slave port Avalon-MM waitrequest signal.
control slave port Avalon-MM write signal. When you assert this signal,
the control port accepts new data from the writedata bus.
control slave port Avalon-MM writedata bus. These input lines are used
for write transfers.
din port Avalon-ST data bus. This bus enables the transfer of pixel data
into the MegaCore function.
din port Avalon-ST endofpacket signal. This signal marks the end of an
Avalon-ST packet.
din port Avalon-ST ready signal. This signal indicates when the MegaCore
function is ready to receive data.
din port Avalon-ST startofpacket signal. This signal marks the start of
an Avalon-ST packet.
din port Avalon-ST valid signal. This signal identifies the cycles when the
port should input data.
din port Avalon-ST data bus. This bus enables the transfer of pixel data
out of the MegaCore function.
dout port Avalon-ST endofpacket signal. This signal marks the end of an
Avalon-ST packet.
dout port Avalon-ST ready signal. The downstream device asserts this
signal when it is able to receive data.
dout port Avalon-ST startofpacket signal. This signal marks the start of
an Avalon-ST packet.
dout port Avalon-ST valid signal. This signal is asserted when the
MegaCore function outputs data.
(1)
(1)
(1)
Description
May 2011 Altera Corporation
(1)
(1)
Chapter 6: Signals
(1)
Interlacer