AD9863BCPZ-50 Analog Devices Inc, AD9863BCPZ-50 Datasheet - Page 21

• Manufacturer Part Number: AD9863BCPZ-50
• Description: IC,RF Modulator/Demodulator,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9863BCPZ-50

• Rf Type: WLL, WLAN
• Features: 12-bit ADC(s), 12-bit DAC(s)
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

this architecture, the AD9863 offers programmable (via the SPI
port), fine (trim) gain and offset adjustment for each DAC.
Also included in the AD9863 are a phase-locked loop (PLL)
clock multiplier and a 1.2 V band gap voltage reference. With
the PLL enabled, a clock applied to the CLKIN2 input is
multiplied internally and generates all necessary internal
synchronization clocks. Each 12-bit DAC provides two
complementary current outputs whose full-scale currents can
be determined from a single external resistor.
An external pin, TxPWRDWN, can be used to power down the
Tx path when not in use, optimizing system power consumption.
Using the TxPWRDWN pin disables clocks and some analog
circuitry, saving both digital and analog power. The power-
down mode leaves the biases enabled to facilitate a quick recov-
ery time, typically <10 µs. In addition, a sleep mode is available
that turns off the DAC output current but leaves all other
circuits active for a modest power savings. An SPI-compliant
serial port is used to program the many features of the AD9863.
Note that in power-down mode, the SPI port is still active.
DAC Equivalent Circuits
The AD9863 Tx path, consisting of dual 12-bit DACs, is shown
in Figure 50. The DACs integrate a high performance TxDAC
core, a programmable gain control through a programmable
gain amplifier (TxPGA), coarse gain control, and offset adjust-
ment and fine gain control to compensate for system mismatches.
Coarse gain applies a gross scaling to either DAC by 1×, (1/2)×,
or (1/11)×. The TxPGA provides gain control from 0 dB to
–20 dB in steps of 0.1 dB and is controlled via the 8-bit TxPGA
setting. A fine gain adjustment of ±4% for each channel is con-
trolled through a 6-bit fine gain register. By default, coarse gain
is 1×, the TxPGA is set to 0 dB, and the fine gain is set to 0%.
The TxDAC core of the AD9863 provides dual, differential,
complementary current outputs generated from the 12-bit data.
The 12-bit dual DACs support update rates up to 200 MSPS.
The differential outputs (IOUT+ and IOUT–) of each dual DAC
are complementary, meaning that they always add up to the
full-scale current output of the DAC, I
performance is achieved when the differential current interface
drives balanced loads or a transformer.
REFERENCE
Figure 50. TxDAC Output Structure Block Diagram
TxDAC
TxDAC
BIAS
OFFSET
OFFSET
DAC
DAC
PGA
PGA
+
+
OUTFS
+
+
+
+
. Optimum ac
+
+
IOUT+A
IOUT–A
IOUT+B
IOUT–B
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The fine gain control provides improved balance of QAM
modulated signals, resulting in improved modulation accuracy
and image rejection.
The independent DAC A and DAC B offset control adds a small
dc current to either IOUT+ or IOUT– (not both). The selection
of which IOUT this offset current is directed toward is
programmable via register setting. Offset control can be used
for suppression of a LO leakage signal that typically results at
the output of the modulator. If the AD9863 is dc-coupled to an
external modulator, this feature can be used to cancel the output
offset on the AD9863 as well as the input offset on the
modulator. The reference circuitry is shown in Figure 51.
Referring to the transfer function of the following equation,
I
default gain setting (0 dB) and is based on a reference current,
I
R
Typically, R
optimal dynamic setting for the TxDACs. Increasing R
factor of 2 proportionally decreases I
I
using the TxPGA gain register, or independently, using the
DAC A/DAC B coarse gain registers.
The TxPGA function provides 20 dB of simultaneous gain
range for both DACs, and it is controlled by writing to the SPI
register TxPGA gain for a programmable full-scale output of
10% to 100% of I
of about 0.1 dB. Internally, the gain is controlled by changing the
main DAC bias currents with an internal TxPGA DAC whose
output is heavily filtered via an on-chip R-C filter to provide
continuous gain transitions. Note that the settling time and
bandwidth of the TxPGA DAC can be improved by a factor of 2
by writing to the TxPGA fast update register.
Each DAC has independent coarse gain control. Coarse gain
control can be used to accommodate different I
DACs. The coarse full-scale output control can be adjusted by using
the DAC A/DAC B coarse gain registers to 1/2 or 1/11 of the
nominal full-scale current.
Fine gain controls and dc offset controls can be used to
compensate for mismatches (for system level calibration),
allowing improved matching characteristics of the two Tx
OUTFSMAX
REF
OUTFSMAX
SET
0.1µF
. I
I
resistor.
OUTFSMAX
REF
is set by the internal 1.2 V reference and the external
is the maximum current output of the DAC with the
of each DAC can be rescaled either simultaneously,
SET
= 64 × (REFIO/R
REFIO
FSADJ
R
SET
is 4 kΩ, which sets I
OUTFSMAX
≥
4kΩ
Figure 51. Reference Circuitry
. The gain curve is linear in dB, with steps
REFERENCE
1.2V
SET
)
OUTFSMAX
OUTFSMAX
REFERENCE BIASES
DAC A AND DAC B
SOURCE ARRAY
CURRENT
to 20 mA, the
I
REF
OUTFS
by a factor of 2.
from the dual
AD9863
I
OUTFSMAX
SET
by a