AD9863BCPZ-50 Analog Devices Inc, AD9863BCPZ-50 Datasheet - Page 35

• Manufacturer Part Number: AD9863BCPZ-50
• Description: IC,RF Modulator/Demodulator,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9863BCPZ-50

• Rf Type: WLL, WLAN
• Features: 12-bit ADC(s), 12-bit DAC(s)
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Read Operations
The readback of registers can be a single or dual data byte
operation. The readback can be configured to use 3-wire or
4-wire and can be formatted with MSB first or LSB first. The
instruction header is written to the device either MSB or LSB
first (depending on the mode) followed by the 8-bit output data,
appropriately MSB or LSB justified. By default, the output data
is sent to the dedicated output pin (SDO). Three-wire operation
SCLK
SCLK
SCLK
SDIO
SDIO
SDIO
SDO
SDO
SEN
SEN
SEN
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Figure 56. 1-Byte Serial Register Readback in MSB First Mode, SDIO BiDir Bit Set Logic High (Default, 3-Wire Mode)
Figure 55. 1-Byte Serial Register Readback in MSB First Mode, SDIO BiDir Bit Set Logic Low (Default, 4-Wire Mode)
Figure 57. 1-Byte Serial Register Readback in LSB First Mode, SDIO BiDir Bit Set Logic Low (Default, 4-Wire Mode)
t
t
t
S
S
S
R/W
R/W
A0
t
t
t
DS
DS
DS
t
t
2/1
2/1
t
A1
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DH
DH
DH
A5
A5
A2
INSTRUCTION HEADER
INSTRUCTION HEADER
INSTRUCTION HEADER
A4
A4
t
t
t
A3
HI
HI
HI
t
t
t
LO
LO
LO
A3
A3
A4
A2
A2
A5
A1
A1
Rev. A | Page 35 of 40
2/1
t
t
CLK
CLK
t
CLK
A0
A0
R/W
D7
D7
D0
t
t
DV
DV
t
can be configured by setting the SDIO BiDir register. In 3-wire
mode, the SDIO pin will become an output pin after receiving
the 8-bit instruction header with a readback request.
Figure 55 shows 4-wire SPI read with MSB first; Figure 56
shows 3-wire read with MSB first; and Figure 57 shows 4-wire
read with LSB first.
DV
D6
D6
D1
OUTPUT REGISTER DATA
OUTPUT REGISTER DATA
D5
D5
OUTPUT REGISTER DATA
D2
D4
D4
D3
D3
D3
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D4
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D2
D2
D5
D1
D1
D6
D0
D0
D7
t
t
H
H
t
H
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AD9863