AD9863BCPZ-50 Analog Devices Inc, AD9863BCPZ-50 Datasheet - Page 32

• Manufacturer Part Number: AD9863BCPZ-50
• Description: IC,RF Modulator/Demodulator,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9863BCPZ-50

• Rf Type: WLL, WLAN
• Features: 12-bit ADC(s), 12-bit DAC(s)
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9863
Register Bit
Register 0x13: I/O Configuration
Register 0x14: I/O Configuration
Register 0x15: Clock
Register 0x16: Clock
Bit 4: TxPGA Fast Update (Mode)
Bit 7: Tx Twos Complement
Bit 6: Rx Twos Complement
Bit 5: Tx Inverse Sample
Bit 1, Bit 0: Interpolation Control
Bit 5: Dig Loop On
Bit 4: SPIFD/HD
Bit 3: SpiTx/ Rx
Bit 2: SpiB12/24
Bit 1: SPI IO Control
Bit 0: SpiClone
Bit 7: PLL_Bypass
Bit 5: ADC Clock Div
Bit 4: Alt Timing Mode
Bit 3: PLL Div5
Bit 2 to Bit 0: PLL Multiplier
Bit 5: PLL to IFACE2
Bit 2: PLL Slow
Description
The TxPGA fast bit controls the update speed of the TxPGA. When fast update mode is enabled, the
TxPGA provides fast gain settling within a few clock cycles, which may introduce spurious signals at
the output of the Tx path. The default setting for this bit is low, and the TxPGA gives a smooth
transition between gain settings. Fast mode is enabled when this bit is set high.
The default data format for Tx data is straight binary. Set this bit high when providing twos
complement Tx data.
The default data format for Rx data is straight binary. Set this bit high when providing twos
complement Rx data.
By default, the transmit data is sampled on the rising edge of the CLKOUT. Setting this bit high
changes this, and the transmit data are sampled on the falling edge.
These register bits control the interpolation rate of the transmit path. The default settings are both
bits low, indicating that both interpolation filters are bypassed. The MSB and LSB are Address Bit 1
and Address Bit 0, respectively. Setting binary 01 provides an interpolation rate of 2×; binary 10
provides an interpolation rate of 4×.
When enabled, this bit enables a digital loop-back mode. The digital loop-back mode provides a
means of testing digital interfaces and functionality at the system level. In digital loop-back mode,
the full-duplex interface must be enabled. (Refer to the Flexible I/O Interface Options section.) The
device accepts data from the digital input bus according to the FD mode timing, and the data is
processed by using the Tx digital path (including any enabled interpolation filter). The processed
data is then output from the Rx path bus.
Control bit to configure full-duplex (high) or half-duplex (low) interface mode. This register, in
combination with the SpiB12/24 register, configures the interface mode of FD, HD12, or HD24. The
register setting is ignored for clone mode operation. By default, this register is set high, and the
device is in FD mode.
Control bit for transmit or receive mode for the half-duplex clock modes. High represents Tx and
low represents Rx.
Control bit for 12-bit or 24-bit modes. High represents 12-bit mode and low represents 24-bit mode.
Use in conjunction with SpiTx/ Rx [Register14, Bit 3] to override external Tx/ Rx pin operation.
Set high when in clone mode (see Flexible I/O Interface Options section for definition of clone
mode). Clk_mode should also be set to Binary 111, such as [Register 01[7:5] = 111.
Setting this bit high bypasses the PLL. When bypassed, the PLL remains active.
By default the ADCs are driven directly from CLKIN1 in normal timing operation or from the PLL
output clock in the alternative timing operation. This bit is used to divide the source of the ADC
clock prior to the ADCs. The default setting is low and performs no division. Setting this bit high
divides the clock by 2.
Table 5 describes two timing modes: the normal timing operation mode and the alternative timing
operation mode. The default configuration is normal timing mode, and the CLKIN1 drives the Rx
path. In alternative timing mode, the PLL output is used to drive the Rx path. The alternative
operation mode is configured by setting this bit high.
The output of the PLL can be divided by 5 by setting this bit high. By default, the PLL directly drives
the Tx digital path with no division of its output.
These bits control the PLL multiplication factor. A default setting is Binary 000, which configures the
PLL to 1× multiplication factor. This register, in combination with the PLL Div5 register, sets the PLL
output frequency. The programmable multiplication factors are
Setting this bit high switches the IFACE2 output signal to the PLL output clock. It is valid only if
Register 0x01, Bit 2 is enabled or if full-duplex mode is configured.
Changes the PLL loop bandwidth; changes profile of the phase noise generated from the PLL clock.
000
001
010
011
100
101 to 111
Rev. A| Page 32 of 40
1×
2×
4×
8×
16×
not used