AD9863BCPZ-50 Analog Devices Inc, AD9863BCPZ-50 Datasheet - Page 23

• Manufacturer Part Number: AD9863BCPZ-50
• Description: IC,RF Modulator/Demodulator,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9863BCPZ-50

• Rf Type: WLL, WLAN
• Features: 12-bit ADC(s), 12-bit DAC(s)
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DIGITAL BLOCK
The AD9863 digital block allows the device to be configured
in various timing and operation modes. The following sec-
tions discuss the flexible I/O interfaces, the clock distribution
block, and the programming of the device through mode pins
or SPI registers.
Table 10. Flexible Data Interface Modes
Mode
Name
HD24
HD12
FD
Clone
Tx Only Mode (Half-Duplex)
AD9863
AD9863
AD9863
AD9863
IFACE1
IFACE2
IFACE3
IFACE1
IFACE2
IFACE3
IFACE1
IFACE2
IFACE3
IFACE1
IFACE2
IFACE3
U[0:11]
U[0:11]
U[0:11]
U[0:11]
L[0:11]
L[0:11]
L[11]
L[11]
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
Tx_A/B DATA
Tx_A/B DATA
Tx_A/B DATA
Tx_A DATA
Tx_B DATA
TxSYNC
TxSYNC
TxSYNC
Tx/Rx
Tx/Rx
Tx/Rx
03604-0-078
03604-0-079
03604-0-080
03604-0-081
DIGITAL
DIGITAL
DIGITAL
DIGITAL
BACK
BACK
BACK
BACK
END
END
END
END
Rx Only Mode (Half-Duplex)
AD9863
AD9863
AD9863
AD9863
IFACE1
IFACE2
IFACE3
IFACE1
IFACE2
IFACE3
IFACE1
IFACE2
IFACE3
IFACE1
IFACE2
IFACE3
U[0:11]
U[0:11]
U[0:11]
L[0:11]
L[0:11]
L[0:11]
L[0:11]
U[11]
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
OUTPUT CLOCK
Rx_A/B DATA
Rx_A/B DATA
Rx_B DATA
Rx_B DATA
Rx_A DATA
Rx_A DATA
RxSYNC
Tx/Rx
Tx/Rx
Tx/Rx
Rev. A | Page 23 of 40
03604-0-082
03604-0-083
03604-0-084
03604-0-085
DIGITAL
DIGITAL
DIGITAL
DIGITAL
BACK
BACK
BACK
BACK
END
END
END
END
Flexible I/O Interface Options
The AD9863 can accommodate various data interface transfer
options (flexible I/O). The AD9863 uses two 12-bit buses, an
upper bus (U12) and a lower bus (L12), to transfer the dual-
channel 12-bit ADC data and dual-channel 12-bit DAC data by
means of interleaved data, parallel data, or a mix of both. Table 10
shows the different I/O configurations of the modes depending
on half-duplex or full-duplex operation. Table 11 and Table 12
summarize the pin configurations vs. the modes.
Concurrent Tx + Rx Mode
(Full-Duplex)
AD9863
IFACE1
IFACE2
IFACE3
U[0:11]
L[0:11]
OUTPUT CLOCK
OUTPUT CLOCK
Rx_A/B DATA
Tx_A/B DATA
TxSYNC
N/A
N/A
N/A
03604-0-086
DIGITAL
BACK
END
General Notes
Rx data rate
Two 12-bit parallel Tx data
Rx data rate
One 12-bit interleaved Rx
Tx data rate
One 12-bit interleaved Tx
Rx data rate
One 12-bit interleaved Rx
Tx data rate
One 12-bit interleaved Tx
Rx data rate
Two 12-bit parallel Rx data
Tx data rate
One 12-bit interleaved Tx
Requires SPI interface to
configure; similar to AD9862
data interface
Two 12-bit parallel Rx data
Tx data rate
= 1 × ADC sample rate
buses
= 1 × ADC sample rate
buses
= 2 × ADC sample rate
data bus
= 2 × ADC sample rate
data bus
= 2 × ADC sample rate
data bus
= 2 × ADC sample rate
data bus
= 1 × ADC sample rate
buses
= 2 × ADC sample rate
data bus
AD9863