AD9863BCPZ-50 Analog Devices Inc, AD9863BCPZ-50 Datasheet - Page 34

• Manufacturer Part Number: AD9863BCPZ-50
• Description: IC,RF Modulator/Demodulator,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9863BCPZ-50

• Rf Type: WLL, WLAN
• Features: 12-bit ADC(s), 12-bit DAC(s)
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9863
Write Operations
The SPI write operation uses the instruction header to config-
ure a 1-byte or 2-byte register write using the 2/ 1 byte setting.
The instruction byte followed by the register data is written
serially into the device through the SDIO pin on rising edges
of the interface clock, SCLK. The data can be transferred MSB
first or LSB first, depending on the setting of the LSB-first
register bit. The write operation is the same, regardless of
SDIO BiDir register setting.
Figure 52 to Figure 54 are examples of writing data into the
device. Figure 52 shows a 1-byte write in MSB-first mode;
Figure 53 shows a 2-byte write in MSB-first mode; and
SCLK
SCLK
SCLK
SDIO
SDIO
SDIO
SEN
SEN
SEN
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t
t
S
S
R/W
A0
INSTRUCTION HEADER (REGISTER N)
INSTRUCTION HEADER (REGISTER N)
t
DS
t
DS
t
t
t
DH
S
DH
A1
R/W
2/1
A2
A5
t
DS
2/1
t
A3
HI
t
A4
t
LO
LO
A4
A5
A3
t
DH
INSTRUCTION HEADER
A5
A2
A4
t
HI
Figure 52. 1-Byte Serial Register Write in MSB-First Mode
Figure 54. 2-Byte Serial Register Write in LSB-First Mode
Figure 53. 2-Byte Serial Register Write in MS-First Mode
2/1
A1
t
t
CLK
CLK
A3
R/W
t
A0
HI
D0
A2
D7
t
D1
LO
D6
Rev. A| Page 34 of 40
REGISTER (N) DATA
A1
REGISTER (N) DATA
t
D2
CLK
D5
D3
A0
D4
D4
D3
D7
Figure 54 shows a 2-byte write in LSB-first mode. Note the
differences between LSB- and MSB-first modes: both the
instruction header and data are reversed, and the second data
byte register location is different. In the default MSB-first
mode, the second data byte is written to a decremented
register address. In LSB-first mode, the second data byte is
written to an incremented register address.
D5
D2
D6
D6
D1
D7
D5
D0 D7
REGISTER DATA
D0
D4
D1
D6
REGISTER (N+1) DATA
REGISTER (N–1) DATA
D3
D2
D5
D3
D4
D2
D4
D3
D1
D5
D2
D6
D0
D1
t
H
D7
D0
t
H
t
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H
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