AD9863BCPZ-50 Analog Devices Inc, AD9863BCPZ-50 Datasheet - Page 24

• Manufacturer Part Number: AD9863BCPZ-50
• Description: IC,RF Modulator/Demodulator,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9863BCPZ-50

• Rf Type: WLL, WLAN
• Features: 12-bit ADC(s), 12-bit DAC(s)
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9863
Table 11 describes AD9863 pin function (when mode pins are used) relative to I/O mode and for half-duplex modes, whether
transmitting or receiving.
Table 11. AD9863 Pin Function vs. Interface Mode (No SPI Cases)
Mode Name
FD
HD12
(Tx/Rx = High)
HD12
(Tx/Rx = Low)
HD24
(Tx/Rx = High)
HD24
(Tx/Rx = Low)
Clone Mode
(Tx/Rx = High)
Clone Mode
(Tx/Rx = Low)
1
Table 12 describes AD9863 pin function (when SPI programming is used) relative to flexible I/O mode and for half-duplex modes,
whether transmitting or receiving.
Table 12. AD9863 Pin Function vs. Interface Mode (Configured through the SPI Registers)
Mode Name
FD
HD12, Tx Mode
HD12, Rx Mode
HD24, Tx Mode
HD24, Rx Mode
Clone Mode,
Tx Mode
Clone Mode,
Rx Mode
Summary of Flexible I/O Modes
FD Mode
The full-duplex (FD) mode can be configured by using mode
pins or with SPI programming. Using the SPI allows additional
configuration flexibility of the device.
FD mode is the only mode that supports full-duplex, receive,
and transmit concurrent operations. The upper 12-bit bus
(U12) is used to accept interleaved Tx data, and the lower 12-bit
bus (L12) is used to output interleaved Rx data. Either the Rx
path or the Tx path (or both) can be independently powered
down using either (or both) the RxPwrDwn and TxPwrDwn
pins. FD mode requires interpolation of 2× or 4×.
Clone mode not available without SPI.
(Tx/Rx = High)
(Tx/Rx = Low)
(Tx/Rx = High)
(Tx/Rx = Low)
(Tx/Rx = High)
(Tx/Rx = Low)
U12 Bus
Interleaved Tx data
Interleaved Tx data
MSB = RxSYNC
Others = three-state
Tx_A data
Rx_B data
x
x
U12 Bus
Interleaved Tx data
Interleaved Tx data
MSB = RxSYNC
Other = three-state
Tx_A data
Rx_B data
Interleaved Tx data
Rx_B data
L12 Bus
Interleaved Rx data
MSB = TxSYNC
Others = three-state
Interleaved Rx data
Tx_B data
Rx_A data
x
x
L12 Bus
Interleaved Rx data
MSB = TxSYNC
others = three-state
Interleaved Tx data
Tx_B data
Rx_A data
MSB = TxSYNC
Others = three-state
Rx_A data
Rev. A| Page 24 of 40
IFACE1
TxSYNC
Tx/Rx = tied high
Tx/Rx = tied low
Tx/Rx = tied high
Tx/Rx = tied low
x
x
IFACE1
TxSYNC
Tx/Rx = tied high
Tx/Rx = tied low
Tx/Rx = tied high
Tx/Rx = tied low
Tx/Rx = tied high
Tx/Rx = tied low
1
The following notes provide a general description of the FD
mode configuration. For more information, refer to Table 15.
Note the following about the Tx path in FD mode:
•
•
•
Interpolation rate of 2× or 4× can be programmed with
mode pins or SPI.
Max DAC update rate = 200 MSPS.
Max Tx input data rate = 80 MSPS/channel (160 MSPS
interleaved).
TxSYNC is used to direct Tx input data.
TxSYNC = high indicates channel Tx_A data.
TxSYNC = low indicates channel Tx_B data.
IFACE2
Buffered Rx Clock
12/24 pin control tied high
12/24 pin control tied low
x
x
12/24 pin control tied high
12/24 pin control tied low
IFACE2
Buffered system
clock
Optional buffered
system clock
Optional buffered
system clock
Optional buffered
system clock
Optional buffered
system clock
Optional buffered
system clock
Optional buffered
system clock
IFACE3
Buffered Tx clock
Buffered Tx clock
Buffered Rx clock
Buffered Tx clock
Buffered Rx clock
Buffered Tx clock
Buffered Rx clock
IFACE3
Buffered Tx clock
Buffered Tx clock
Buffered Rx clock
Buffered Tx clock
Buffered Rx clock
x
x