AD9863BCPZ-50 Analog Devices Inc, AD9863BCPZ-50 Datasheet - Page 26

• Manufacturer Part Number: AD9863BCPZ-50
• Description: IC,RF Modulator/Demodulator,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9863BCPZ-50

• Rf Type: WLL, WLAN
• Features: 12-bit ADC(s), 12-bit DAC(s)
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9863
The following notes provide a general description of the clone
mode configuration. For more information, refer to Table 15.
Note the following about the Tx path in clone mode:
•
•
•
•
Note the following about the Rx path in clone mode:
•
•
•
•
Table 13. Mode Pin Names and Functions
Pin Name
RxPWRDWN
TxPWRDWN
Tx/Rx (IFACE1)
ADC_LO_PWR
SPI_Bus_Enable
(SPI_CS)
FD/HD
12/24
Only valid for HD
mode
Interp0 and
Interp1
Interpolation rate of 2× or 4× can be programmed with
mode pins or SPI.
Max DAC update rate = 200 MSPS.
Max Tx input data rate = 80 MSPS/channel (160 MSPS
interleaved).
TxSYNC is used to direct Tx input data.
TxSYNC = high indicates channel Tx_A data.
TxSYNC = low indicates channel Tx_B data.
Buffered Tx clock output (from IFACE3 pin) uses one
rising edge per interleaved Tx sample.
ADC CLK Div register can be used to divide down the
clock driving the ADC, which accepts up to 50 MHz.
Max ADC sampling rate = 50 MSPS.
Output data rate = ADC sample rate, that is, two 12-bit
parallel outputs per one buffer Rx clock output cycle.
The Rx_A output data is output on L12 bus; the Rx_B
output data is output on U12 bus.
Duration
Permanent
Permanent
Permanent only for
HD Flex I/O interface
Defined at reset or
power-up
Defined at reset or
power-up
Defined at reset or
power-up
Defined at reset or
power-up
Defined at reset or
power-up
Function
When high, digital clocks to the Rx block are disabled. Analog circuitry that requires <10 µs
to power up is powered off.
When high, digital clocks to Tx block are disabled (PLL remains powered). Analog circuitry
that requires <10 µs to power up is powered off.
When high, digital clocks to the Tx block are disabled (PLL remains powered to maintain
output clock with an optional SPI shutoff). Tx analog circuitry remains powered up unless
Tx_PwrDwn is asserted.
When low, digital clocks to Rx block are disabled. Rx analog circuitry remains powered up
unless Rx_PwrDwn is asserted.
When enabled, this bit scales the ADC power-down by 40%.
This function is controlled through the SPI_CS pin. This pin must remain low to maintain
mode pin functionality (the SPI port remains nonfunctional). This pin must be high when
coming out of reset to enable the SPI.
Configures the flex I/O for FD or HD mode. This control applies only if the SPI bus is disabled.
If the flex I/O bus is in HD mode, this bit is used to configure parallel or interleaved data
mode. This control applies only if the SPI bus is disabled.
The Interp1 and Interp0 bits configure the PLL and the interpolation rate to 1× [00], 2× [01],
or 4× [10]. This control applies only if the SPI bus is disabled.
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Configuring with Mode Pins
The flexible interface can be configured with or without the
SPI, although more options and flexibility are available when
using the SPI to program the AD9863. Mode pins can be used
to power down sections of the device, reduce overall power
consumption, configure the flexible I/O interface, and
program the interpolation setting. The SPI register map,
which provides many more options, is presented in the
Configuring with SPI section.
Mode Pins/Power-Up Configuration Options
Mode pins provide various options that are configurable at
power-up. Control pins also provide options for power-down
modes. The logic value of the configuration mode pins are
latched when the device is brought out of reset (upon the rising
edge of RESET ). The mode pin names and functions are listed
in Table 13. Table 14 provides a detailed description of the
mode pins.