AD9863BCPZ-50 Analog Devices Inc, AD9863BCPZ-50 Datasheet - Page 37

• Manufacturer Part Number: AD9863BCPZ-50
• Description: IC,RF Modulator/Demodulator,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9863BCPZ-50

• Rf Type: WLL, WLAN
• Features: 12-bit ADC(s), 12-bit DAC(s)
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 21. Interface Pins (IFACE1, IFACE2, IFACE3) Configuration Definition for Flexible Interface Operation
Clock
Mode Pin
CLKIN1,
CLKIN2
IFACE1
IFACE2
IFACE3
The Tx clock output frequency depends on whether the data is
in interleaved or parallel (noninterleaved) configuration. Modes
1, 2, 7, 8, and 10 use Tx interleaved data and require either 2×
or 4× interpolation to be enabled.
•
•
•
The Rx clock does not depend on whether the data is
interleaved or parallel, but it does depends on the configuration
of the timing mode: normal or alternative.
•
•
DAC update rate = CLKIN2 × PLL setting.
Noninterleaved Tx data clock frequency = CLKIN2 × PLL
setting × 1/(interpolation rate).
Interleaved Tx data clock frequency = 2 × CLKIN2 × PLL
setting × 1/(interpolation rate).
Normal timing mode, Rx clock frequency = CLKIN1 ×
ADC div factor (if enabled).
Alternative timing mode, Rx clock frequency = CLKIN2 ×
PLL setting × ADC div factor (if enabled).
1
Full-Duplex
Independent
TxSync
Buff_CLKIN1
Tx Clock
CLKIN2
CLKIN1
2
Internally
Tied
Together
RxSync
1. ALTERNATE TIMING MODE: REG 0x15, BIT 4
2. PLL MULTIPLICATION SETTING: REG 0x15, BITS 2–0
3. PLL OUTPUT DIVIDE BY 5; REG 0x15, BIT 3
4. Rx PATH DIVIDE BY 2: REG 0x15, BIT 5
5. PLL BYPASS PATH: REG 0x15, BIT 7
6. INTERP CONTROL, Tx/Rx INV IFACE3, CLK MODE, INV IFACE2, FD/HD, 12/24
1, 2, 4, 8, 16
4T
Half-Duplex, 24-Bit
Independent
Tx/ Rx
Optional CLKOUT
Tx
Clock
1
2
Figure 58. Clock Distribution Block Diagram
4R
Rx
Clock
1, 5
3
1, 2
Rev. A | Page 37 of 40
4
5T
Internally Tied
Together
Tx
Clock
5
50MHz MAX
5R
Rx
Clock
An optional CLKOUT from IFACE2 is available as a stable
system clock running at the CLKIN1 frequency or the TxDAC
update rate, which is equal to CLKIN2 × PLL setting. Setting
the enable IFACE2 clkout register [Register 0x01, Bit 2] enables
the IFACE2 optional clock output. In FD mode the IFACE2 pin
always acts as a clock output; the enable IFACE2 pin can be
used to invert the IFACE2 output.
Configuration
The AD9863 timing for the transmit path and for the receive
path depend on the mode setting and various programmable
options. The registers that affect the output clock timing and
data input/output timing are Clk_Mode [2:0], enable IFACE2
clkout, inv clkout (IFACE3), Tx inverse sample, interpolation
control, PLL bypass, ADC clock div, alt timing mode, PLL Div5,
PLL multiplier, and PLL to IFACE2. The Clk_Mode register is
presented previously.
Table 22 shows the other register bits that are used to configure
the output clock timing and data latching options available in
the AD9863.
DIGITAL
DIGITAL
BLOCK
BLOCK
Rx
Tx
7T
Half-Duplex, 12-Bit
Independent
Tx/ Rx
Optional CLKOUT
Tx
Clock
Rx
PATH
Tx
PATH
FORMATTER
7R
Rx
Clock
OUTPUT
CLOCK
6
8T
Internally Tied
Together
Tx
Clock
IFACE2
IFACE3
8R
Rx
Clock
10T
Clone Mode
Independent
Tx/ Rx
Optional
CLKOUT
Tx
Clock
AD9863
10R
Rx
Clock