ADUC7121BBCZ-RL Analog Devices Inc, ADUC7121BBCZ-RL Datasheet - Page 29
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ADUC7121BBCZ-RL
Manufacturer Part Number
ADUC7121BBCZ-RL
Description
PRECISION ANALOG MCU I.C
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.ADUC7121BBCZ.pdf
(96 pages)
Specifications of ADUC7121BBCZ-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
41.78MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
126KB (63K x 16)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x12b, D/A 4x12b
Oscillator Type
Internal
Operating Temperature
-10°C ~ 95°C
Package / Case
108-LFBGA, CSPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADUC7121BBCZ-RL
ADUC7121BBCZ-RLTR
ADUC7121BBCZ-RLTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADUC7121BBCZ-RL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
The input level for PGA is limited to a maximum value of
AVDD − 1.2 V and minimum value of 0.1 V to ensure that the
amplifiers are not saturated. The input buffer is a rail-to-rail
buffer. It can accept signals from 0.15 to AVDD − 0.15 V. Both
the positive and negative input buffers can be bypassed indepen-
dently by setting ADCCON Bits[15:14].
Typical Operation
Once configured via the ADC control and channel selection
registers, the ADC converts the analog input and provides a
12-bit result in the ADC data register.
The top four bits are the sign bits, and the 12-bit result is placed
from Bit 27 to Bit 16, as shown in Figure 15. Again, note that, in
fully differential mode, the result is represented in twos comple-
ment format, and when in pseudo differential and single-ended
modes, the result is represented in straight binary format.
Timing
Figure 16 provides details of the ADC timing. Users control the
ADC clock speed and the number of acquisition clocks in the
ADCCON MMR. By default, the acquisition time is eight clocks
and the clock divider is two. The number of additional clocks
(such as bit trial or write) is set to 19, giving a sampling rate of
774 kSPS. For conversion on the temperature sensor, the ADC
acquisition time is automatically set to 16 clocks and the ADC
clock divider is set to 32. When using multiple channels, including
the temperature sensor, the timing settings revert back to the
user-defined settings after reading the temperature sensor channel.
ADC CLOCK
TEMPERATURE SENSOR
The ADuC7121 provides a voltage output from an on-chip
band gap reference proportional to absolute temperature. This
voltage output can also be routed through the front-end ADC
multiplexer (effectively, an additional ADC channel input),
31
SIGN BITS
CONV
ADC
ADCDAT
START
BUSY
27
Figure 15. ADC Result Format
Figure 16. ADC Timing
ACQ
12-BIT ADC RESULT
BIT TRIAL
ADCSTA = 0
WRITE
ADC INTERRUPT
DATA
16 15
ADCSTA = 1
0
Rev. 0 | Page 29 of 96
facilitating an internal temperature sensor channel that
measures die temperature.
The internal temperature sensor is not designed for use as an
absolute ambient temperature calculator. It is intended for use as an
approximate indicator of the temperature of the ADuC7121 die.
The typical temperature coefficient is −0.707 mV/°C.
ADC MMR Interface
The ADC is controlled and configured via a number of MMRs
(see Table 28) that are described in detail in this section.
Table 28. ADC MMRs
Name
ADCCON
ADCCP
ADCCN
ADCSTA
ADCDAT
ADCRST
ADCGN
ADCOF
PGA_GN
1250
1200
1150
1100
1050
1000
–20
Description
ADC control register. ADCCON allows the programmer to
enable the ADC peripheral, to select the mode of
operation of the ADC (either single-ended, pseudo
differential, or fully differential mode), and to select the
conversion type (see
Table
ADC positive channel selection register.
ADC negative channel selection register.
ADC status register. ADCSTA indicates when an ADC
conversion result is ready. The ADCSTA register contains
only one bit, ADCREADY (Bit 0), representing the status
of the ADC. This bit is set at the end of an ADC
conversion generating an ADC interrupt. It is cleared
automatically by reading the ADCDAT MMR. When the
ADC is performing a conversion, the status of the ADC
can be read externally via the ADC
This pin is high during a conversion. When the
conversion is finished, ADC
information can be available on P0.2 (see the
General-Purpose Input/Output section) if enabled in the
GP0CON register.
ADC data result register. ADCDAT holds the 12-bit ADC
result, as shown in Figure 15.
ADC reset register. ADCRST resets all of the ADC
registers to their default values.
ADC gain calibration register for non-PGA channels.
ADC offset calibration register for all ADC channels.
Gain of PGA_PADC0 and PGA_PADC1.
Figure 17. ADC Output vs. Temperature
29
0
).
20
TEMPERATURE (°C)
40
Busy
returns to low. This
60
Busy
function of Pin C3.
ADuC7121
80
100