ADUC7121BBCZ-RL Analog Devices Inc, ADUC7121BBCZ-RL Datasheet - Page 47

• Manufacturer Part Number: ADUC7121BBCZ-RL
• Description: PRECISION ANALOG MCU I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7121BBCZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 126KB (63K x 16)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 95°C
• Package / Case: 108-LFBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADUC7121BBCZ-RL; ADUC7121BBCZ-RLTR

The operating mode, clocking mode, and programmable clock
divider are controlled via two MMRs, PLLCON (see Table 65) and
POWCON (see Table 66). PLLCON controls the operating
mode of the clock system, and POWCON controls the core
clock frequency and the power-down mode.
External Crystal Selection
To switch to an external crystal, use the following procedure:
1.
2.
3.
4.
In noisy environments, noise can couple to the external crystal
pins, and PLL may lose lock momentarily. A PLL interrupt is
provided in the interrupt controller. The core clock is immediately
halted, and this interrupt is serviced only when the lock is restored.
In case of crystal loss, the watchdog timer should be used. During
initialization, a test on the RSTSTA register can determine if the
reset came from the watchdog timer.
1
WATCHDOG
32.768kHz ±3%
TIMERS
TIMER
Enable the Timer2 interrupt and configure it for a timeout
period of >120 μs.
Follow the write sequence to the PLLCON register, setting
the MDCLK bits to 01 and clearing the OSEL bit.
Force the part into nap mode by writing the correct write
sequence to the POWCON register.
When the part is interrupted from nap mode by the Timer2
interrupt source, the clock source has switched to the
external clock.
CORE
OSCILLATOR
INT. 32kHz
Figure 32. Clocking System
OCLK 32.768kHz
PLL
I
2
C
1
CD
41.78MHz
UCLK
AT POWER-UP
OSCILLATOR
P1.4/ECLK
CRYSTAL
/2
CD
HCLK
PERIPHERALS
ANALOG
MDCLK
XTALO
XTALI
P1.4/XCLK
Rev. 0 | Page 47 of 96
Example Source Code
//ensures timer value loaded
//enable T2 interrupt
// set core into nap mode
External Clock Selection
To switch to an external clock on P1.4 (of the
P1.4/PWM1/ECLK/XCLK/PLAI[8] pin), configure P1.4 in
Mode 2. The external clock can be up to 41.78 MHz.
Example Source Code
//ensures timer value loaded
//enable T2 interrupt
Power Control System
A choice of operating modes is available on the ADuC7121.
Table 63 describes what part of the ADuC7121 is powered on in
the different modes and indicates the power-up time. Table 64
gives some typical values of the total current consumption (analog
+ digital supply currents) in the different modes, depending on
the clock divider bits. The ADC is turned off. Note that these
values also include current consumption of the regulator and other
parts on the test board on which these values were measured.
while ((T2VAL == t2val_old) || (T2VAL > 3))
IRQEN = 0x10;
PLLKEY1 = 0xAA;
PLLCON = 0x01;
PLLKEY2 = 0x55;
POWKEY1 = 0x01;
POWCON = 0x27;
POWKEY2 = 0xF4;
while ((T2VAL == t2val_old) || (T2VAL > 3))
IRQEN = 0x10;
PLLKEY1 = 0xAA;
PLLCON = 0x03; //Select external clock
PLLKEY2 = 0x55;
POWKEY1 = 0x01;
POWCON = 0x27; // Set Core into Nap mode
POWKEY2 = 0xF4;
T2LD = 5;
TCON = 0x480;
T2LD = 5;
TCON = 0x480;
ADuC7121