ADUC7121BBCZ-RL Analog Devices Inc, ADUC7121BBCZ-RL Datasheet - Page 56

• Manufacturer Part Number: ADUC7121BBCZ-RL
• Description: PRECISION ANALOG MCU I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7121BBCZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 126KB (63K x 16)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 95°C
• Package / Case: 108-LFBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADUC7121BBCZ-RL; ADUC7121BBCZ-RLTR

ADuC7121
Name:
Address:
Default value:
Access:
Table 76. GPxDAT MMR Bit Designations
Bit
31:24
23:16
15:8
7:0
GPxSET Registers
The GPxSET registers provide a data set for the Port x registers.
Name:
Address:
Default value:
Access:
Name:
Address:
Default value:
Access:
Name:
Address:
Default value:
Access:
Name:
Address:
Default value:
Access:
Description
Direction of the data.
Set to 1 by the user to configure the GPIO pin as an
output.
Cleared to 0 by the user to configure the GPIO pin as
an input.
Port x data output.
Reflect the state of Port x pins at reset (read only).
Port x data input (read only).
GP3DAT
0xFFFF0D50
0x000000XX
Read and write
GP0SET
0xFFFF0D24
0x000000XX
Write only
GP1SET
0xFFFF0D34
0x000000XX
Write only
GP2SET
0xFFFF0D44
0x000000XX
Write only
GP3SET
0xFFFF0D54
0x000000XX
Write only
Rev. 0 | Page 56 of 96
Table 77. GPxSET MMR Bit Designations
Bit
31: 24
23:16
15:0
GPxCLR Registers
The GPxCLR registers are data clear for Port x registers.
Name:
Address:
Default value:
Access:
Name:
Address:
Default value:
Access:
Name:
Address:
Default value:
Access:
Name:
Address:
Default value:
Access:
Table 78. GPxCLR MMR Bit Designations
Bit
31:24
23:16
15:0
GPxOCE Registers
Open-collector functionality is available on the following GPIO
pins: P1.7, P1.6, Port 2, and Port 3.
Data Port x set bit.
Set to 1 by the user to set the bit on Port x; also sets
Description
Reserved.
the corresponding bit in the GPxDAT MMR.
Cleared to 0 by user; does not affect the data out.
Reserved.
Description
Reserved.
Set to 1 by the user to clear bit on Port x; also clears
the corresponding bit in the GPxDAT MMR.
Cleared to 0 by user; does not affect the data output.
Reserved.
Data Port x clear bit.
GP0CLR
0xFFFF0D28
0x000000XX
Write only
GP1CLR
0xFFFF0D38
0x000000XX
Write only
GP2CLR
0xFFFF0D48
0x000000XX
Write only
GP3CLR
0xFFFF0D58
0x000000XX
Write only