ADUC7121BBCZ-RL Analog Devices Inc, ADUC7121BBCZ-RL Datasheet - Page 65

• Manufacturer Part Number: ADUC7121BBCZ-RL
• Description: PRECISION ANALOG MCU I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7121BBCZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 126KB (63K x 16)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 95°C
• Package / Case: 108-LFBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADUC7121BBCZ-RL; ADUC7121BBCZ-RLTR

I
This 16-bit MMR is I
Name:
Address:
Default value:
Access:
Table 88 I2CxMSTA MMR Bit Designations
Bit
15:11
10
9
8
7
6
5
4
3
2
1:0
2
C Master Status Register
Name
I2CBBUSY
I2CMRxFO
I2CMTC
I2CMNA
I2CMBUSY
I2CAL
I2CMNA
I2CMRXQ
I2CMTXQ
I2CMTFSTA
I2C0MSTA, I2C1MSTA
0xFFFF0884, 0xFFFF0904
0x0000, 0x0000
Read only
2
C status register in master mode.
Description
Reserved. These bits are reserved.
I
This bit is set to 1 when a start condition is detected on the I
This bit is cleared when a stop condition is detected on the bus.
Master receiver (Rx) FIFO overflow.
This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.
This bit is cleared in all other conditions.
I
This bit is set to 1 when a transmission is complete between the master and the slave with which it was
communicating. If the I2CMCENI bit in I2CxMCTL is set, an interrupt is generated when the I2CMTC bit is set.
Clear this interrupt source.
I
This bit is set to 1 when a no acknowledge condition is received by the master in response to a data write transfer. If
the I2CNACKENI bit in I2CxMCTL is set, an interrupt is generated when the I2CMNA bit is set.
This bit is cleared in all other conditions.
I
Set to 1 when the master is busy processing a transaction.
Cleared if the master is ready or if another master device has control of the bus.
I
This bit is set to 1 when the I
I2CxMCTL is set, an interrupt is generated when the I2CAL bit is set.
This bit is cleared in all other conditions.
I
This bit is set to 1 when a no acknowledge condition is received by the master in response to an address. If the
I2CNACKENI bit in I2CxMCTL is set, an interrupt is generated when the I2CMNA bit is set.
This bit is cleared in all other conditions.
I
This bit is set to 1 when data enters the Rx FIFO. If the I2CMRENI in I2CxMCTL is set, an interrupt is generated.
This bit is cleared in all other conditions.
I
This bit goes high if the transmitter (Tx) FIFO is empty or only contains one byte and the master has transmitted an
address + write. If the I2CMTENI bit in I2CxMCTL is set, an interrupt is generated when the I2CMTXQ bit is set.
This bit is cleared in all other conditions.
I
00 = I
01 = one byte in master Tx FIFO.
10 = one byte in master Tx FIFO.
11 = I
2
2
2
2
2
2
2
2
2
C bus busy status bit.
C transmission complete status bit.
C master no acknowledge data bit.
C master busy status bit.
C arbitration lost status bit.
C master no acknowledge address bit.
C master receive request bit.
C master transmit request bit.
C master Tx FIFO status bits.
2
2
C master Tx FIFO empty.
C master Tx FIFO full.
2
C master is unsuccessful in gaining control of the I
Rev. 0 | Page 65 of 96
2
C bus.
2
C bus. If the I2CALENI bit in
ADuC7121