ADUC7121BBCZ-RL Analog Devices Inc, ADUC7121BBCZ-RL Datasheet - Page 76

• Manufacturer Part Number: ADUC7121BBCZ-RL
• Description: PRECISION ANALOG MCU I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7121BBCZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 126KB (63K x 16)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -10°C ~ 95°C
• Package / Case: 108-LFBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADUC7121BBCZ-RL; ADUC7121BBCZ-RLTR

ADuC7121
PROGRAMMABLE LOGIC ARRAY (PLA)
The ADuC7121 integrates a fully programmable logic array (PLA)
that consists of two independent but interconnected PLA blocks.
Each block consists of eight PLA elements, giving each part a
total of 16 PLA elements.
Each PLA element contains a dual input lookup table that can
be configured to generate any logic output function based on
two inputs and a flip-flop. This is represented in Figure 36.
In total, 32 GPIO pins are available on each ADuC7121 for the
PLA. These include 16 input pins and 16 output pins, which need
Table 99. Element Input/Output
Element
0
1
2
3
4
5
6
7
0
1
2
3
Figure 36. PLA Element
A
B
Input
P2.7
P2.2
P0.6
P0.7
P0.1
P0.0
P1.1
P1.0
LOOKUP
TABLE
PLA Block 0
Output
P3.0
P3.1
P3.2
P3.3
P1.7
P1.6
P2.5
P2.4
4
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Element
8
9
10
11
12
13
14
15
to be configured in the GPxCON register as PLA pins before using
the PLA. Note that the comparator output is also included as
one of the 16 input pins, and that the JTAG TDI and TDO pins
are included as PLA outputs. If you want to use JTAG program-
ming or debugging, then you cannot use the JTAG TDI and
TDO pins as PLA outputs.
The PLA is configured via a set of user MMRs. The output(s)
of the PLA can be routed to the internal interrupt system, to
the ADC
16 PLA output pins.
The two blocks can be interconnected as follows:
•
•
Output of Element 15 (Block 1) can be fed to Input 0 of
Mux 0 of Element 0 (Block 0).
Output of Element 7 (Block 0) can be fed to the Input 0 of
Mux 0 of Element 8 (Block 1).
CONVST
signal of the ADC, to an MMR, or to any of the
Input
P1.4
P1.5
P0.5
P0.4
P2.1
P2.0
P2.3
P2.6
PLA Block 1
Output
P3.4
P3.5
P3.6
P3.7
P0.3
P0.2
P1.3
P1.2