EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 127

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

Figure 2–82. Stratix II GX IOE in DDR Input I/O Configuration
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
October 2007
Column, Row,
Interconnect
or Local
All input signals to the IOE can be inverted at the IOE.
This signal connection is only allowed on dedicated DQ function pins.
This signal is for dedicated DQS function pins only.
The optional PCI clamp is only available on column I/O pins.
ioe_clk[7..0]
Figure
DQS Local
2–82:
Bus (2)
sclr/spreset
clkin
ce_in
aclr/apreset
Chip-Wide Reset
Input Register
Input Register
D
CLRN/PRN
ENA
D
CLRN/PRN
ENA
Input RegisterDelay
I
nput Pin to
Q
Q
Note (1)
Stratix II GX Device Handbook, Volume 1
D
ENA
CLRN/PRN
To DQS Logic
Latch
Block (3)
Q
VCCIO
Stratix II GX Architecture
VCCIO
PCI Clamp (4)
Bus-Hold
Termination
Circuit
On-Chip
Programmable
Pull-Up
Resistor
2–119