EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 175

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

Altera Corporation
June 2009
Absolute V
for a
pin
Rise/fall time
Duty cycle
Peak-to-peak
differential
input voltage
Spread-
spectrum
clocking
On-chip
termination
resistors
V
coupled)
V
coupled)
Rref
Transceiver Clocks
Calibration
block clock
frequency
Calibration
block minimum
power-down
pulse width
Time taken for
one-time
calibration
fixedclk
clock
frequency
Table 4–6. Stratix II GX Transceiver Block AC Specification (Part 2 of 6)
I C M
I C M
Description
Symbol /
(12)
REFCLK
(AC
(DC
(12)
(4)
M I N
PCI Express
Receiver
Detect
Adaptive
Equalization
(AEQ)
Conditions
-0.5%
-3 Speed Commercial
0.25
Min
-0.3
200
0 to
2.5
40
30
10
30
-
-
-
Speed Grade
115 ±20%
1200 ±5%
2000 ±1%
125
Typ
0.2
-
-
-
-
-
-
-
-
-
-0.5%
2000
Max
0.55
0 to
125
125
60
33
8
-
-
-
-
-0.5%
-4 Speed Commercial
and Industrial Speed
0.25
Min
-0.3
200
0 to
2.5
40
30
10
30
-
-
-
115 ±20%
1200 ±5%
2000 ±1%
Stratix II GX Device Handbook, Volume 1
Grade
Typ
125
0.2
-
-
-
-
-
-
-
-
-
DC and Switching Characteristics
-0.5%
2000
Max
0.55
0 to
125
125
60
33
8
-
-
-
-
-0.5%
-5 Speed Commercial
0.25
Min
-0.3
200
0 to
40
30
10
30
-
-
-
-
Speed Grade
115 ±20%
1200 ±5%
2000 ±1%
125
Typ
0.2
-
-
-
-
-
-
-
-
-
-0.5%
2000
Max
0.55
0 to
125
60
33
8
-
-
-
-
-
4–5
MHz
MHz
MHz
Unit
kHz
mV
mV
ms
UI
ns
%
V
Ω
V
Ω