EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 55

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

Figure 2–34. LAB-Wide Control Signals
Altera Corporation
October 2007
Dedicated Row LAB Clocks
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
6
6
load acts as a preset when the asynchronous load data input is tied high.
When the asynchronous load/preset signal is used, the labclkena0
signal is no longer available.
The LAB row clocks [5..0] and LAB local interconnect generate the
LAB-wide control signals. The MultiTrack™ interconnects have
inherently low skew. This low skew allows the MultiTrack interconnects
to distribute clock and control signals in addition to data.
Figure 2–34
6
labclk0
clock signals per LAB.
There are two unique
shows the LAB control signal generation circuit.
or asyncload
or labpreset
labclkena0
labclk1
labclkena1
Stratix II GX Device Handbook, Volume 1
labclk2
labclkena2
syncload
Stratix II GX Architecture
labclr0
labclr1
2–47
synclr