EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 86

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

TriMatrix Memory
Figure 2–55. M-RAM Block LAB Row Interface
Note to
(1)
2–78
Stratix II GX Device Handbook, Volume 1
Only R24 and C16 interconnects cross the M-RAM block boundaries.
Figure
LABs in Row
M-RAM Boundary
2–55:
Row Unit Interface Allows LAB
Rows to Drive Port A Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
LAB Interface
Blocks
L0
L1
L2
L3
L4
L5
Port A
Note (1)
M-RAM Block
Row Unit Interface Allows LAB
Rows to Drive Port B Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
Port B
R0
R1
R2
R3
R4
R5
LABs in Row
M-RAM Boundary
Altera Corporation
October 2007