EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 82

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

TriMatrix Memory
Figure 2–51. M4K RAM Block Control Signals
2–74
Stratix II GX Device Handbook, Volume 1
Dedicated
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
The R4, C4, and direct link interconnects from adjacent LABs drive the
M4K RAM block local interconnect. The M4K RAM blocks can
communicate with LABs on either the left or right side through these row
resources or with LAB columns on either the right or left with the column
resources. Up to 16 direct link input connections to the M4K RAM block
are possible from the left adjacent LABs and another 16 possible from the
right adjacent LAB. M4K RAM block outputs can also connect to left and
right LABs through direct link interconnect.
RAM block to logic array interface.
6
clock_a
clock_b
clocken_a
clocken_b
renwe_a
Figure 2–52
renwe_b
Altera Corporation
shows the M4K
aclr_a
October 2007
aclr_b