EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 14

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

Transceivers
Figure 2–4. Transmitter PLL Block
Note to
(1)
2–6
Stratix II GX Device Handbook, Volume 1
Dedicated Local
Dedicated Local
REFCLK 1
REFCLK 0
The global clock line must be driven by an input pin.
Figure
Inter-Transceiver Block
Routing (IQ[4:0])
Inter-Transceiver Block
Routing (IQ[4:0])
To Inter-Transceiver
Block Line
From PLD
From PLD
2–4:
÷
÷
2
/2 2
The transmitter PLLs support data rates up to 6.375 Gbps. The input clock
frequency is limited to 622.08 MHz. An optional pll_locked port is
available to indicate whether the transmitter PLL is locked to the
reference clock. Both transmitter PLLs have a programmable loop
bandwidth parameter that can be set to low, medium, or high. The loop
bandwidth parameter can be statically set in the Quartus II software.
Table 2–2
Table 2–2. Transmitter PLL Specifications
Input reference frequency range
Note (1)
Multiplication factor (W)
lists the adjustable parameters in the transmitter PLL.
Data rate support
INCLK
INCLK
Parameter
Bandwidth
PFD
PFD
÷
up
dn
up
dn
÷
m
m
CP+LF
CP+LF
VCO
VCO
Transmitter PLL 0
Transmitter PLL 1
600 Mbps to 6.375 Gbps
1, 4, 5, 8, 10, 16, 20, 25
50 MHz to 622.08 MHz
÷
÷
Low, medium, or high
L
L
Specifications
Transmitter PLL0 Clock
Transmitter PLL1 Clock
High-Speed
High-Speed
Altera Corporation
Transmitter PLL Clock
High-Speed
October 2007