EP3C5E144A7N Altera, EP3C5E144A7N Datasheet - Page 114

Cyclone III

EP3C5E144A7N

Manufacturer Part Number
EP3C5E144A7N
Description
Cyclone III
Manufacturer
Altera
Datasheet

Specifications of EP3C5E144A7N

Family Name
Cyclone III
Number Of Logic Blocks/elements
5136
# I/os (max)
94
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
5136
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
EQFP
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C5E144A7N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP3C5E144A7N
Manufacturer:
XILINX
0
Part Number:
EP3C5E144A7N
Manufacturer:
ALTERA
0
6–14
Figure 6–6. Cyclone III Device Family HSTL I/O Standard Termination
Figure 6–7. Cyclone III Device Family SSTL I/O Standard Termination
Differential I/O Standard Termination
Cyclone III Device Handbook, Volume 1
Termination
Termination
and without
Calibration
On-Board
OCT with
External
Termination
and without
Termination
Calibration
OCT with
On-Board
External
Cyclone III Device
Family Series OCT
Transmitter
Differential I/O standards typically require a termination resistor between the two
signals at the receiver. The termination resistor must match the differential load
impedance of the bus
The Cyclone III device family supports differential SSTL-2 and SSTL-18, differential
HSTL-18, HSTL-15, and HSTL-12, PPDS, LVDS, RSDS, mini-LVDS, and differential
LVPECL.
Cyclone III Device
Family Series OCT
Transmitter
Transmitter
Transmitter
50
50
25
SSTL Class I
HSTL Class I
50
50
50
V REF
50
V REF
50
V REF
50
50
V REF
50
V TT
V TT
V TT
V TT
(Figure 6–8
Receiver
Receiver
Receiver
Receiver
and
Cyclone III Device
Family Series OCT
Figure
Cyclone III Device
Family Series OCT
Transmitter
Transmitter
Transmitter
Transmitter
25
25
Chapter 6: I/O Features in the Cyclone III Device Family
6–9).
V TT
V TT
25
50
HSTL Class II
50
SSTL Class II
50
50
V TT
V TT
50
50
V REF
© December 2009 Altera Corporation
50
50
V REF
Termination Scheme for I/O Standards
50
50
V TT
50
V REF
V REF
V TT
50
V TT
V TT
Receiver
Receiver
Receiver
Receiver

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