EP3C5E144A7N Altera, EP3C5E144A7N Datasheet - Page 222

• Manufacturer Part Number: EP3C5E144A7N
• Description: Cyclone III
• Manufacturer: Altera

Specifications of EP3C5E144A7N

• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 5136
• # I/os (max): 94
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 5136
• Ram Bits: 423936
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: EQFP
• Lead Free Status / Rohs Status: Compliant

9–62
Table 9–19. JTAG CONFIG_IO (without JTAG_PROGRAM) Instruction Flows
Cyclone III Device Handbook, Volume 1
FACTORY
ACTIVE_DISENGAGE
CONFIG_IO
JTAG Boundary Scan Instructions (no
JTAG_PROGRAM)
JTAG Instruction
I/O Reconfiguration
Use the CONFIG_IO instruction to reconfigure the I/O configuration shift register
(IOCSR) chain. This instruction allows you to perform board-level testing prior to
configuring the Cyclone III device family or waiting for a configuration device to
complete configuration. After the configuration is interrupted and JTAG testing is
complete, the part must be reconfigured using the PULSE_NCONFIG JTAG
instruction or by pulsing the nCONFIG pin low.
You can issue the CONFIG_IO instruction any time during user mode. The
CONFIG_IO instruction cannot be issued when nCONFIG pin is asserted low (during
power up) or immediately after issuing a JTAG instruction that triggers
reconfiguration. For more information about the wait-time for issuing the CONFIG_IO
instruction, refer to
When using CONFIG_IO instruction, you must meet the following timing restrictions:
■
■
■
Table 9–18. Wait Time for Issuing the CONFIG_IO Instruction
Use the ACTIVE_DISENGAGE instruction with CONFIG_IO instruction to interrupt
configuration.
CONFIG_IO usage scenarios.
Wait time after the nCONFIG pin is released
Wait time after PULSE_NCONFIG or ACTIVE_ENGAGE is
issued
CONFIG_IO instruction cannot be issued during the nCONFIG pin low
Observe 230 μs minimum wait time after any of the following conditions are met:
■
■
■
Wait 230 μs after power up with nCONFIG pin high before issuing the CONFIG_IO
instruction (or wait for the nSTATUS pin to go high)
nCONFIG pin goes high
Issuing the PULSE_NCONFIG instruction
Issuing the ACTIVE_ENGAGE instruction, before issuing the CONFIG_IO
instruction
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Table 9–19
NA
PS
O
R
O
Table
Configuration Scheme and Current State of the Cyclone III Device Family
Prior to User Mode
Wait Time
Configuration)
(Interrupting
FPP
NA
O
R
O
9–18.
lists the sequence of instructions to use for various
NA
AS
O
R
O
AP
(4)
NA
O
R
O
PS
NA
O
R
O
(Note 1)
User Mode
FPP
NA
O
R
O
(Part 1 of 2)
NA
AS
© December 2009 Altera Corporation
O
R
O
NA
AP
(4)
O
O
R
230 ms
230 ms
Time
NA
PS
—
—
Configuration Features
R
Power Up
FPP AS
NA
—
—
R
—
NA NA
—
R
AP
(4)
NA
—
—