EP3C5E144A7N Altera, EP3C5E144A7N Datasheet - Page 141
![Cyclone III](/photos/37/16/371628/144pin_eqfp_sml.jpg)
EP3C5E144A7N
Manufacturer Part Number
EP3C5E144A7N
Description
Cyclone III
Manufacturer
Altera
Datasheet
1.EP3C5E144A7N.pdf
(274 pages)
Specifications of EP3C5E144A7N
Family Name
Cyclone III
Number Of Logic Blocks/elements
5136
# I/os (max)
94
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
5136
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
EQFP
Lead Free Status / Rohs Status
Compliant
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Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
Design Guidelines
Figure 7–16. Cyclone III Device Family High-Speed I/O Timing Budget
Note to
(1) The equation for the high-speed I/O timing budget is:
Design Guidelines
Differential Pad Placement Guidelines
Board Design Considerations
© December 2009
Period
Figure
=
7–16:
0.5
f
f
Internal Clock Period
Altera Corporation
×
TCCS
Figure 7–16
For more information, refer to the
Device Data Sheet
This section provides guidelines for designing with the Cyclone III device family.
To maintain an acceptable noise level on the V
restrictions on the placement of single-ended I/O pins in relation to differential pads.
For more information about the guidelines on placing single-ended pads with respect
to differential pads in the Cyclone III device family, refer to the
Features
This section explains how to achieve the optimal performance from the Cyclone III
device family I/O interface and ensure first-time success in implementing a
functional design with optimal signal quality. You must consider the critical issues of
controlled impedance of traces and connectors, differential routing, and termination
techniques to get the best performance from the Cyclone III device family.
Use the following general guidelines for improved signal quality:
■
■
■
■
+
RSKM
Base board designs on controlled differential impedance. Calculate and compare
all parameters, such as trace width, trace thickness, and the distance between two
differential traces.
Maintain equal distance between traces in differential I/O standard pairs as much
as possible. Routing the pair of traces close to each other maximizes the
common-mode rejection ratio (CMRR).
Longer traces have more inductance and capacitance. These traces must be as
short as possible to limit signal integrity issues.
Place termination resistors as close to receiver input pins as possible.
chapter.
+
SW
shows the Cyclone III device family high-speed I/O timing budget.
0.5 × TCCS
+
RSKM
chapters in volume 2 of the Cyclone III Device Handbook.
RSKM
+
0.5
×
TCCS.
Cyclone III Device Data Sheet
SW
(Note 1)
CCIO
supply, you must observe some
RSKM
Cyclone III Device Handbook, Volume 1
0.5 × TCCS
and
Cyclone III Device I/O
Cyclone III LS
7–17
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