EP3C5E144A7N Altera, EP3C5E144A7N Datasheet - Page 270
![Cyclone III](/photos/37/16/371628/144pin_eqfp_sml.jpg)
EP3C5E144A7N
Manufacturer Part Number
EP3C5E144A7N
Description
Cyclone III
Manufacturer
Altera
Datasheet
1.EP3C5E144A7N.pdf
(274 pages)
Specifications of EP3C5E144A7N
Family Name
Cyclone III
Number Of Logic Blocks/elements
5136
# I/os (max)
94
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
5136
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
EQFP
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 270 of 274
- Download datasheet (6Mb)
12–4
Table 12–3. IEEE Std. 1149.1 (JTAG) Instructions Supported by Cyclone III Device Family (Part 2 of 2)
Cyclone III Device Handbook, Volume 1
APFC_BOOT_ADDR (2),
FACTORY
KEY_PROG_VOL
KEY_CLR_VREG
Notes to
(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
(2) For more information about how to use CONFIG_IO, EN_ACTIVE_CLK, DIS_ACTIVE_CLK, ACTIVE_DISENGAGE,
(3) APFC_BOOT_ADDR instruction is not supported in Cyclone III LS devices.
(4) For Cyclone III LS devices only. For more information about how to program the security key into the volatile registers, refer to the
ACTIVE_ENGAGE and APFC_BOOT_ADDR instructions for Cyclone III device family, refer to the
Remote System Upgrades in Cyclone III Devices
Configuration, Design Security, and Remote System Upgrades in Cyclone III Devices
JTAG Instruction
Table
(4)
12–3:
1
(4)
(4)
The IEEE Std. 1149.1 BST circuitry is enabled upon device power-up. You can perform
BST on Cyclone III device family before, after, and during configuration. Cyclone III
device family supports the BYPASS, IDCODE and SAMPLE instructions during
configuration without interrupting configuration. To send all other JTAG instructions,
interrupt the configuration using the CONFIG_IO instruction except for active
configuration schemes in which the ACTIVE_DISENGAGE instruction is used instead.
The CONFIG_IO instruction allows you to configure I/O buffers via the JTAG port,
and when issued, interrupts configuration. This instruction allows you to perform
board-level testing prior to configuring Cyclone III device family. Alternatively, you
can wait for the configuration device to complete configuration. After configuration is
interrupted and JTAG BST is complete, you must reconfigure the part via JTAG
(PULSE_NCONFIG instruction) or by pulsing nCONFIG low.
When you perform JTAG boundary-scan testing before configuration, the nCONFIG
pin must be held low.
(3)
Instruction Code
10 0111 0000
10 1000 0001
01 1010 1101
00 0010 1001
chapter.
Clears the volatile verify register which signifies the validity of the
volatile keys stored in the registers. You must clear the volatile verify
register by issuing this command whenever you attempt to program a
new volatile key. This instruction must be asserted for at least 10 TCK
cycles.
Places the 22-bit active boot address register between the TDI and
TDO pins, allowing a new active boot address to be serially shifted into
TDI and into the active parallel (AP) flash controller. In remote system
upgrade, the PFC_BOOT_ADDR instruction sets the boot address for
the factory configuration.
Enables access to all other JTAG instructions (other than BYPASS,
SAMPLE/PRELOAD and EXTEST instructions, which are supported
upon power up). This instruction also clears the device configuration
data and advanced encryption standard (AES) volatile key.
Used to enter and store the security key into volatile registers. When
this instruction is executed, TDI is connected to a 512-bit volatile key
scan chain. TDO is not connected to the end of this scan chain.
Chapter 12: IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family
chapter.
Description
Configuration, Design Security, and
IEEE Std. 1149.1 BST Operation Control
© December 2009 Altera Corporation
Related parts for EP3C5E144A7N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![EP3C5](/images/no-image3.png)
Part Number:
Description:
Cyclone III Device Data Sheet
Manufacturer:
ALTERA [Altera Corporation]
Datasheet:
![DK-CYCII-2C20N](/photos/9/20/92074/mfgdk-cycii-2c20nboard_tmb.jpg)
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610IPC-25](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-30](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-12](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10A](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![P85C224-66](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP320PC](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP2A15B724C7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet: