EP3C5E144A7N Altera, EP3C5E144A7N Datasheet - Page 17
![Cyclone III](/photos/37/16/371628/144pin_eqfp_sml.jpg)
EP3C5E144A7N
Manufacturer Part Number
EP3C5E144A7N
Description
Cyclone III
Manufacturer
Altera
Datasheet
1.EP3C5E144A7N.pdf
(274 pages)
Specifications of EP3C5E144A7N
Family Name
Cyclone III
Number Of Logic Blocks/elements
5136
# I/os (max)
94
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
5136
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
EQFP
Lead Free Status / Rohs Status
Compliant
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Chapter 1: Cyclone III Device Family Overview
Cyclone III Device Family Features
Table 1–1. Cyclone III Device Family Features
© December 2009
Cyclone III LS
Cyclone III
Family
EP3CLS100
EP3CLS150
EP3CLS200
EP3CLS70
EP3C120
EP3C10
EP3C16
EP3C25
EP3C40
EP3C55
EP3C80
Device
Altera Corporation
EP3C5
■
■
Cyclone III device family supports vertical migration that allows you to migrate your
device to other devices with the same dedicated pins, configuration pins, and power
pins for a given package-across device densities. This allows you to optimize device
density and cost as your design evolves.
Table 1–1
Wide collection of pre-built and verified IP cores from Altera and Altera
Megafunction Partners Program (AMPP) partners
Supports high-speed external memory interfaces such as DDR, DDR2,
SDR SDRAM, and QDRII SRAM
■
Elements
119,088
100,448
150,848
198,464
10,320
15,408
24,624
39,600
55,856
81,264
70,208
Auto-calibrating PHY feature eases the timing closure process and eliminates
variations with PVT for DDR, DDR2, and QDRII SRAM interfaces
5,136
Logic
lists Cyclone III device family features.
M9K Blocks
Number of
126
260
305
432
333
483
666
891
46
46
56
66
Total RAM
1,161,216
2,396,160
2,810,880
3,981,312
3,068,928
4,451,328
6,137,856
8,211,456
423,936
423,936
516,096
608,256
Bits
Multipliers
18 x 18
126
156
244
288
200
276
320
396
23
23
56
66
PLLs
2
2
4
4
4
4
4
4
4
4
4
4
Cyclone III Device Handbook, Volume 1
Global Clock
Networks
10
10
20
20
20
20
20
20
20
20
20
20
Maximum
User I/Os
182
182
346
215
535
377
429
531
413
413
413
413
1–3
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