EP3C5E144A7N Altera, EP3C5E144A7N Datasheet - Page 226
![Cyclone III](/photos/37/16/371628/144pin_eqfp_sml.jpg)
EP3C5E144A7N
Manufacturer Part Number
EP3C5E144A7N
Description
Cyclone III
Manufacturer
Altera
Datasheet
1.EP3C5E144A7N.pdf
(274 pages)
Specifications of EP3C5E144A7N
Family Name
Cyclone III
Number Of Logic Blocks/elements
5136
# I/os (max)
94
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
5136
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
EQFP
Lead Free Status / Rohs Status
Compliant
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Cyclone III Device Handbook, Volume 1
1
To revert the clock source back to the configuration oscillator, issue the
DIS_ACTIVE_CLK instruction. After you issue the DIS_ACTIVE_CLK instruction,
you must continue to clock the CLKUSR pin for 10 clock cycles. Otherwise, even
toggling the nCONFIG pin does not revert the clock source and reconfiguration does
not occur. A POR reverts the clock source back to the configuration oscillator.
Toggling the nCONFIG pin or driving the JTAG state machine to the reset state does
not revert the clock source.
EN_ACTIVE_CLK
The EN_ACTIVE_CLK instruction causes the CLKUSR pin signal to replace the internal
oscillator as the clock source. When using the EN_ACTIVE_CLK instruction, the
internal oscillator must be enabled for the clock change to occur. After this instruction
is issued, other JTAG instructions can be issued while the CLKUSR pin signal remains
as the clock source. The clock source is only reverted back to the internal oscillator by
issuing the DIS_ACTIVE_CLK instruction or a POR.
DIS_ACTIVE_CLK
The DIS_ACTIVE_CLK instruction breaks the CLKUSR enable latch set by the
EN_ACTIVE_CLK instruction and causes the clock source to revert back to the internal
oscillator. After the DIS_ACTIVE_CLK instruction is issued, you must continue to
clock the CLKUSR pin for 10 clock cycles.
The CLKUSR pin must be clocked at two times the expected DCLK frequency. The
CLKUSR pin allows a maximum frequency of 80 MHz (40 MHz DCLK).
Changing the Start Boot Address of the AP Flash
In the AP configuration scheme, for Cyclone III devices only, you can change the
default configuration boot address of the parallel flash memory to any desired
address using the APFC_BOOT_ADDR JTAG instruction.
APFC_BOOT_ADDR
The APFC_BOOT_ADDR instruction is for Cyclone III devices only and allows you to
define a start boot address for the parallel flash memory in the AP configuration
scheme.
This instruction shifts in a start boot address for the AP flash. When this instruction
becomes the active instruction, the TDI and TDO pins are connected through a 22-bit
active boot address shift register. The shifted-in boot address bits get loaded into the
22-bit AP boot address update register, which feeds into the AP controller. The content
of the AP boot address update register can be captured and shifted-out of the active
boot address shift register from TDO.
The boot address in the boot address shift register and update register are shifted to
the right (in the LSB direction) by two bits versus the intended boot address. The
reason for this is that the two LSB of the address are not accessible. When this boot
address is fed into the AP controller, two 0s are attached in the end as LSB, thereby
pushing the shifted-in boot address to the left by two bits, which become the actual
AP boot address the AP controller gets.
If you have enabled the remote update feature, the APFC_BOOT_ADDR instruction sets
the boot address for the factory configuration only.
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
© December 2009 Altera Corporation
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