EP3C5E144A7N Altera, EP3C5E144A7N Datasheet - Page 139
![Cyclone III](/photos/37/16/371628/144pin_eqfp_sml.jpg)
EP3C5E144A7N
Manufacturer Part Number
EP3C5E144A7N
Description
Cyclone III
Manufacturer
Altera
Datasheet
1.EP3C5E144A7N.pdf
(274 pages)
Specifications of EP3C5E144A7N
Family Name
Cyclone III
Number Of Logic Blocks/elements
5136
# I/os (max)
94
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
5136
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
EQFP
Lead Free Status / Rohs Status
Compliant
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Part Number
Manufacturer
Quantity
Price
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Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
True Output Buffer Feature
Figure 7–13. Differential HSTL Class II Interface
Note to
(1) PLL output clock pins do not support differential HSTL Class II I/O standard.
True Output Buffer Feature
Programmable Pre-Emphasis
Figure 7–14. The Output Signal with Pre-Emphasis
© December 2009
Figure
Output Buffer (1)
7–13:
Altera Corporation
Figure 7–13
Cyclone III device family true differential transmitters offer programmable
pre-emphasis—you can choose to turn it on or off. The default setting is on.
The programmable pre-emphasis boosts the high frequencies of the output signal to
compensate the frequency-dependant attenuation of the transmission line to
maximize the data eye opening at the far-end receiver. Without pre-emphasis, the
output current is limited by the V
transmitter. At high frequency, the slew rate may not be fast enough to reach full V
before the next edge; this may lead to pattern dependent jitter. With pre-emphasis, the
output current is momentarily boosted during switching to increase the output slew
rate. The overshoot produced by this extra switching current is different from the
overshoot caused by signal reflection. This overshoot happens only during switching,
and does not produce ringing.
Figure 7–14
shows the differential HSTL Class II interface.
shows the differential output signal with pre-emphasis.
Negative channel (n)
V
Positive channel (p)
TT
50 Ω
V
TT
50 Ω
Z 0 = 50 Ω
Z 0 = 50 Ω
OD
specification and the output impedance of the
V
TT
Overshoot
Undershoot
V
50 Ω
OD
V
TT
50 Ω
Cyclone III Device Handbook, Volume 1
Receiver
7–15
OD
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