LPC2364HBD100 NXP Semiconductors, LPC2364HBD100 Datasheet - Page 26

• Manufacturer Part Number: LPC2364HBD100
• Description: LPC2364HBD100/LQFP100/TRAYBDP/
• Manufacturer: NXP Semiconductors
• Series: LPC2300r

Specifications of LPC2364HBD100

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, Ethernet, I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 34K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Processor Series: LPC23
• Core: ARM7TDMI-S
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

NXP Semiconductors
LPC2364_65_66_67_68_6
Product data sheet
7.18.1 Features
7.19.1 Features
7.19 I
The I
The I
and one word select signal. The basic I
master, and one slave. The I
separate transmit and receive channel, each of which can operate as either a master or a
slave.
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
S-bus serial I/O controllers
I
I
devices connected to the same bus lines.
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
The interface has separate input/output channels each of which can operate in master
or slave mode.
Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
Mono and stereo audio data supported.
The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1,
48) kHz.
Configurable word select period in master mode (separately for I
Two 8-word FIFO data buffers are provided, one for transmit and one for receive.
Generates interrupt requests when buffer levels cross a programmable boundary.
Two DMA requests, controlled by programmable buffer levels. These are connected
to the GPDMA block.
Controls include reset, stop and mute options separately for I
2
2
2
2
C0 is a standard I
C1 and I
S-bus provides a standard communication interface for digital audio applications.
S-bus specification defines a 3-wire serial bus using one data line, one clock line,
2
C-bus can be used for test and diagnostic purposes.
2
C2 use standard I/O pins and do not support powering off of individual
Rev. 06 — 1 February 2010
2
C compliant bus interface with open-drain pins.
2
S interface on the LPC2364/65/66/67/68 provides a
2
S connection has one master, which is always the
LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
2
S input and I
2
S input and output).
© NXP B.V. 2010. All rights reserved.
2
S output.
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