CS1D-BC042D Omron, CS1D-BC042D Datasheet - Page 375

• Manufacturer Part Number: CS1D-BC042D
• Description: CS1D Dual CPU Exp
• Manufacturer: Omron

Specifications of CS1D-BC042D

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Power OFF Operation
9-3-1
Disabling Power Interruption Processing in the Program
340
Instruction Execution for Power Interruptions
1,2,3...
Note
2. If the Power OFF Detection Delay Time is set (0 to 10 ms in 1-ms incre-
If power is interrupted and the interruption is confirmed when the CPU Unit is
operating in RUN or MONITOR mode, the instruction currently being executed
will be completed (see note) and the following power interruption processing
will be performed.
1. The current instruction can be completed only when the time required to
2. Power OFF interrupt tasks are supported only by Single CPU Systems and
Areas of the program can be protected from power interruptions so that the
instructions will be executed before the CPU Unit even if the power supply is
interrupted. This is achieved by using the DISABLE INTERRUPTS (DI(693))
and ENABLE INTERRUPTS (EI(694)) instructions. Using these instructions
must be enabled in the PLC Setup.
The following procedure is used.
1. Insert DI(693) before the program section to be protected to disable inter-
2. Set the Disable Setting for Power OFF Interrupts in A530 to A5A5 hex to
First Cycle Flag
• If the power OFF interrupt task has not been enabled, the CPU Unit will
• If the power OFF interrupt task has been enabled, the task will be exe-
A20011
ments) in the PLC Setup, the CPU reset signal will turn ON while the inter-
nal power supply is maintained and the CPU Unit will be reset.
Note a) Power OFF interrupt tasks cannot be used in Duplex CPU Sys-
be reset immediately.
cuted and then the CPU Unit will be reset immediately.
complete execution is less than or equal to the processing time after power
interruption detection (10 ms
the instruction is not completed within this time, it will be interrupted and
the above processing will be performed.
cannot be used in Duplex CPU Systems.
rupts and then place EI(694) after the section to enable interrupts.
enable disabling power interruption processing.
Note A530 is normally cleared when power is turned OFF. To prevent this,
b) Power OFF interrupt tasks are supported only by Single CPU Sys-
the IOM Hold Bit (A50012) must be turned ON and the PLC Setup
must be set to maintain the setting of the IOM Hold Bit at Startup, or
the following type of instruction must be included at the beginning of
the program to set A530 to A5A5 hex.
tems.
tems. However, the CPU reset signal will turn ON and the CPU will
be reset after the power OFF interrupt task has been executed.
Make sure that the power OFF interrupt task will finish executing
within 10 ms minus the Power OFF Detection Delay Time = pro-
cessing time after power OFF. The 5-V internal power supply will
be maintained only for 10 ms after power OFF is detected.
MOV
#A5A5
A530
power interruption detection delay time). If
Set A530 to A5A5 Hex at the
beginning of the program to enable
disabling power interruption
processing.
Section 9-3