LAN89218AQ SMSC, LAN89218AQ Datasheet
LAN89218AQ
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LAN89218AQ Summary of contents
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... Interfaces to most 32-bit and 16-bit embedded CPU’s Integrated checksum offload engine Efficient architecture with low CPU overhead AEC-Q100 compliant — SMSC’s TrueAuto™ parts are tested to meet or exceed the requirements of the AEC-Q100 automotive qualification standards Applications Diagnostic interface ...
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... LAN89218AQ (Tray) FOR 100-PIN, TQFP LEAD-FREE ROHS COMPLIANT PACKAGE WITH E3 FINISH (MATTE TIN) LAN89218AQR (Tape & Reel) FOR 100-PIN, TQFP LEAD-FREE ROHS COMPLIANT PACKAGE WITH E3 FINISH (MATTE TIN) This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit TrueAuto™ ...
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... General Purpose Timer (GP Timer 3.9 EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.9.1 MAC Address Auto-Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.9.2 EEPROM Host Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.10 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.10.1 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.10.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.10.3 Internal PHY Power-Down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.11 Detailed Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.11.1 Power-On Reset (POR SMSC LAN89218 3 DATASHEET Revision 1.3 (02-23-10) ...
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... Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.7.1 Re-starting Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.7.2 Disabling Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.7.3 Half vs. Full-Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.8 HP Auto-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Chapter 5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.1 Register Nomenclature and Access Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.2 RX and TX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 4 DATASHEET Datasheet SMSC LAN89218 ...
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... PHY Identifier 125 5.5.4 PHY Identifier 126 5.5.5 Auto-negotiation Advertisement 126 5.5.6 Auto-negotiation Link Partner Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.5.7 Auto-negotiation Expansion 128 5.5.8 Mode Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.5.9 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.5.10 Special Control/Status Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 SMSC LAN89218 5 DATASHEET Revision 1.3 (02-23-10) ...
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... Power Consumption (Device and System Components 147 7.6 DC Electrical Specifications 148 7.7 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Chapter 8 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 8.1 100-TQFP Package 152 Chapter 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Chapter 10 Further Information 155 Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 6 DATASHEET Datasheet SMSC LAN89218 ...
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... Figure 6.5 PIO Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Figure 6.6 TX Data FIFO Direct PIO Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Figure 6.7 nRESET Reset Pin Timing 143 Figure 6.8 EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Figure 8.1 100-Pin TQFP Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 SMSC LAN89218 7 DATASHEET Revision 1.3 (02-23-10) ...
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... Table 7.3 Power Consumption Device and System Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 7.4 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Table 7.5 I/O Buffer Characteristics 148 Table 7.6 100BASE-TX Transceiver Characteristics 150 Table 7.7 10BASE-T Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 8 DATASHEET Datasheet SMSC LAN89218 ...
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... High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet Table 7.8 LAN89218 Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 8.1 100-Pin TQFP Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Table 9.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 SMSC LAN89218 9 DATASHEET Revision 1.3 (02-23-10) ...
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... Ethernet wakeup events. The device can be removed from the low power state via a host processor command. The SMSC LAN89218 integrated 10/100 MAC/PHY controller performs the function of translating parallel data from a host controller into Ethernet packets. The LAN89218 Ethernet MAC/PHY controller is designed and optimized to function in an embedded environment ...
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... LAN911x family, in order to support HP Auto-MDIX, other components such as the magnetics and the passive components around the magnetics need to change. Supporting these changes does require a minor PCB change. Refer to the SMSC website for additional application details. SMSC LAN89218 ...
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... Configurable TX FIFO TX Checksum Offload Engine 10/100 TX Status FIFO Ethernet RX Status FIFO MAC MIL - RX Elastic Buffer - 128 bytes Configurable RX FIFO MIL - TX Elastic Buffer – 2 kbytes Figure 1.2 Internal Block Diagram 12 DATASHEET Datasheet EEPROM (Optional) EEPROM Controller 10/100 Ethernet LAN PHY SMSC LAN89218 ...
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... The interrupt line can be configured as an open-drain output to facilitate the sharing of interrupts with other devices. In addition, a programmable interrupt de-assertion interval is provided. SMSC LAN89218 13 DATASHEET Revision 1.3 (02-23-10) ...
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... LAN89218. An external PME (Power Management Event) interrupt is provided to indicate detection of a wakeup event. 1.11 General Purpose Timer The general-purpose timer has no dedicated function within the LAN89218 and may be programmed to issue a timed interrupt. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 14 DATASHEET Datasheet SMSC LAN89218 ...
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... The package designators are: lll - Lot Sequence Code (optional Chip Revision Number yy - last two digits of Assembly Year ww - Assembly Work Week tttttttttttt - Tracking Number ( characters Country of Original Abbreviation (Optional - characters Free Symbol SMSC LAN89218 LAN89218AQ lllryyww tttttttttttt cc Figure 2.1 Pin Configuration (Top View) 15 DATASHEET 50 D10 ...
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... This signal has the same timing characteristics as the address inputs. Note: This signal is pulled low internally and may be left unconnected or connected to ground for compatibility with earlier devices. 16 DATASHEET Datasheet DESCRIPTION SMSC LAN89218 ...
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... Note: The pin names for the twisted pair pins shown above apply to a normal connection Auto- MDIX is enabled and a reverse connection is detected reverse connection is manually selected, the input pins become outputs, and vice-versa, as indicated in the descriptions. SMSC LAN89218 Table 2.2 LAN Interface Signals BUFFER ...
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... EEPROM. This signal cannot function as a general-purpose input. Note: When the EEPROM interface is not Note: This pin must not be pulled low DATASHEET Datasheet DESCRIPTION used, the EECLK pin must be left unconnected. external resistor or driven low externally under any conditions. SMSC LAN89218 ...
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... Wakeup Indicator PME Auto-MDIX Enable AMDIX_EN 10/100 Selector SPEED_SEL No Connect NC Pull-Down PD (Reserved) SMSC LAN89218 Table 2.4 System and Power Signals BUFFER NUM TYPE PINS ICLK 1 External 25 MHz Crystal Input. This pin can also be connected to single-ended TTL oscillator (CLKIN). If this method is implemented, XTAL2 should be left unconnected ...
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... P 2 +1.8 V from internal core regulator. Both pins must be connected together externally. Each pin requires a 0.01 µF decoupling capacitor. In addition, pin 3 requires a bulk 10uF capacitor (<2 Ω ESR) in parallel Ground for internal digital logic 20 DATASHEET Datasheet DESCRIPTION (Note 2.1) SMSC LAN89218 ...
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... Note 2.1 These pins must not be used to supply power to other external devices. Note 2.2 This pin must not be used to supply power to other external devices. SPEED_SEL SPEED 0 10 Mbps 1 100 Mbps SMSC LAN89218 BUFFER NUM TYPE PINS P 1 +1.8 V Power from the internal PLL regulator. ...
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... D12 71 NC GND_IO 72 IRQ VDD_IO 73 AMDIX_EN D11 74 SPEED_SEL D10 DATASHEET Datasheet PIN NUM PIN NAME 76 FIFO_SEL 77 VSS_A 78 TPO- 79 TPO+ 80 VSS_A 81 VDD_A 82 TPI- 83 TPI VDD_A 86 VSS_A 87 EXRES1 88 VSS_A 89 VDD_A 90 END_SEL nRD 93 nWR 94 nCS 95 nRESET 96 GND_IO 97 VDD_IO 98 GPIO0/nLED1 99 GPIO1/nLED2 100 GPIO2/nLED3 SMSC LAN89218 ...
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... Output 8 mA symmetrical drive O8 50 µA (typical) internal pull- µA (typical) internal pull-down PD Analog input AI Analog output AO Analog bi-directional AIO Crystal oscillator input pin ICLK Crystal oscillator output pin OCLK SMSC LAN89218 Table 2.7 Buffer Types DESCRIPTION 23 DATASHEET Revision 1.3 (02-23-10) ...
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... Interface) port which is internal to the LAN89218. The MAC CSR's also provide a mechanism for accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 24 DATASHEET Datasheet SMSC LAN89218 ...
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... After sensing the collision, the remote station will back off its transmission. The MAC continues sending the jam to make other stations defer transmission. The MAC only generates this collision-based back pressure when it receives a new frame, in order to avoid any late collisions. SMSC LAN89218 25 DATASHEET ...
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... This allows the packet to be received, and then processed by host software transmitted on the network. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Figure 3.1 VLAN Frame 26 DATASHEET Datasheet Figure 3.1, SMSC LAN89218 ...
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... Control Register" If the frame fails the filter, the Ethernet MAC function does not receive the packet. The host has the option of accepting or ignoring the packet. MCPAS PRMS INVFILT SMSC LAN89218 for more information on this register. Table 3.1 Address Filtering Modes HO HPFILT ...
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... For all filtering modes, when MCPAS is set, all multicast frames are accepted. When the PRMS bit is set, all frames are accepted regardless of their destination address. This includes all broadcast frames as well. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 28 DATASHEET Datasheet SMSC LAN89218 ...
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... Note 3.3 When wake-up frame detection is enabled via the WUEN bit of the Control and Status the state of the Disable Broadcast Frame (BCAST) bit in the Register. SMSC LAN89218 WUCSR—Wake-up Control and Status Table 3.2, "Wake-Up Frame Filter Register Structure" Register, a broadcast wake-up frame will wake-up the device despite ...
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... FILTER I BYTE MASK DESCRIPTION Table 3.4 Table 3.4 Filter i Command Bit Definitions FILTER i COMMANDS Table 3.5 describes the Filter i Offset bit fields. 30 DATASHEET Datasheet Filter 1 Reserved Filter 0 Command Command Filter 0 Offset Filter 0 CRC-16 Filter 2 CRC-16 shows the Filter I command register. SMSC LAN89218 ...
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... The device will also accept a multicast frame, as long as it detects the 16 duplications of the MAC address. If the MAC address of a node is 00h 11h 22h 33h 44h 55h, then the MAC scans for the following data sequence in an Ethernet: Frame. SMSC LAN89218 Table 3.5 Filter i Offset Bit Definitions FILTER I OFFSET DESCRIPTION Table 3 ...
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... L3 packet. The VLAN1 tag register is used by the RXCOE to indicate what protocol type used to indicate the existence of a VLAN tag. This value is typically 8100h. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Frame Data Calculate Checksum Figure 3.2 RXCOE Checksum Calculation 32 DATASHEET Datasheet Figure 3. SMSC LAN89218 ...
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... Figure 3.4 Ethernet Frame with VLAN Tag {DSAP, SSAP, CTRL, OUI[23:16 DST SRC 1DWORD Figure 3.5 Ethernet Frame with Length Field and SNAP Header SMSC LAN89218 L3 Packet Calculate Checksum Figure 3.3 Type II Ethernet Frame L3 Packet Calculate Checksum {OUI[15:0], PID[15:0 Packet Calculate Checksum 33 DATASHEET ...
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... RXCOE. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications {OUI[15:0], PID[15:0 Packet Calculate Checksum {OUI[15:0], PID[15:0 Packet Calculate Checksum COE_CR—Checksum Offload Engine Control Register 34 DATASHEET Datasheet Section 3.13.3) enables the SMSC LAN89218 ...
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... Note: The data checksum calculation must not begin in the MAC header (first 14 bytes the last 4 bytes of the TX packet. Note: The TX checksum cannot be inserted in the MAC header (first 14 bytes the last 4 bytes of the TX packet. SMSC LAN89218 Register) and vice versa. These functions cannot be enabled COE_CR—Checksum Offload Engine Control Table 3 ...
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... High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 3". In this example the host writes the packet data to the ethernet controller in Section 3.12.2, "TX Command Format". Table 3.7 TX Checksum Preamble DESCRIPTION 36 DATASHEET Datasheet Section Figure 3.24 shows how these SMSC LAN89218 ...
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... FIFO access byte ordering under various endianess and word swap settings. Refer to Section 3.7.5 for additional details. Note: All internal busses of the LAN89218 are 32-bits wide with little endian byte ordering. SMSC LAN89218 Section 5.3.9, "HW_CFG—Hardware Configuration Register," 37 DATASHEET Table 3 ...
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... Host Data Bus Figure 3.8 Host Data Path Diagram 3.10. and Table 3.9 illustrate the byte ordering applied by the endian logic for 38 DATASHEET Datasheet 102. Figure 3.8 illustrates the order in RX/TX Data FIFO Direct Access (FIFO_SEL = 1) SMSC LAN89218 ...
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... High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet 32-BIT BIG ENDIAN END_SEL = 1 INTERNAL ORDER MSB A[ HOST DATA BUS SMSC LAN89218 WORD_SWAP = Don’t Care 32-BIT LITTLE ENDIAN MSB LSB Figure 3.9 32-bit Byte Ordering 39 DATASHEET END_SEL = 0 INTERNAL ORDER LSB ...
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... High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 16-BIT LITTLE ENDIAN MSB LSB A[ A[ 16-BIT LITTLE ENDIAN MSB LSB A[ A[ Figure 3.10 16-Bit Byte Ordering 40 DATASHEET Datasheet END_SEL = 0 INTERNAL ORDER LSB HOST DATA BUS END_SEL = 0 INTERNAL ORDER LSB HOST DATA BUS SMSC LAN89218 ...
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... INT_STS Register. The GPT_INT hardware interrupt can only be set if the GPT_INT_EN bit is set. GPT_INT is a sticky bit (R/WC); i.e., once the GPT_INT bit is set, it can only be cleared by writing a ‘1’ to the bit. SMSC LAN89218 Host Data Bus D[31:24] ...
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... EPC_BSY bit is cleared. In all cases the host must wait for EPC_BSY to clear before modifying the E2P_CMD register. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications provides an explanation of the supported EEPROM 42 DATASHEET Datasheet 115. Section 5.3.23, "E2P_CMD SMSC LAN89218 ...
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... The host can disable the EEPROM interface through the GPIO_CFG register. When the interface is disabled, the EEDIO and ECLK signals can be used as general-purpose outputs, or they may be used to monitor internal MII signals. SMSC LAN89218 illustrates the host accesses required to perform an EEPROM Read ...
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... EECLK EEDIO (OUTPUT) 1 EEDIO (INPUT) Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Section 5.3.23, "E2P_CMD – EEPROM Command Register," Figure 3.12 EEPROM ERASE Cycle Figure 3.13 EEPROM ERAL Cycle 44 DATASHEET Datasheet t CSL t CSL SMSC LAN89218 ...
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... Disable” command is sent, or until power is cycled. Note: The EEPROM device will power-up in the erase/write-disabled state. Any erase or write operations will fail until an Erase/Write Enable command is issued. EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) SMSC LAN89218 Figure 3.14 EEPROM EWDS Cycle 1 ...
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... EECS EECLK EEDIO (OUTPUT EEDIO (INPUT) Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Figure 3.16 EEPROM READ Cycle Figure 3.17 EEPROM WRITE Cycle Figure 3.18 EEPROM WRAL Cycle 46 DATASHEET Datasheet t CSL CSL D0 t CSL D0 SMSC LAN89218 ...
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... Supported EEPROM operations are described in these sections. 3.9.2.4 EEPROM Timing Refer to Section 6.9, "EEPROM Timing," on page 144 SMSC LAN89218 Cycles", shown below, shows the number of EECLK cycles required for Table 3.10 Required EECLK Cycles REQUIRED EECLK CYCLES for a detailed description of these registers. ...
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... Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Table 7.3, “Power Consumption Device and System and Table 7.3, “Power Consumption Device and System Components,” DATASHEET Datasheet SMSC LAN89218 ...
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... Upon detection, the WUPS field in PMT_CTRL will be set to a 01b. Note 3.10 The PME interrupt status bit on the INT_STS register (PME_INT) is set regardless of the setting of PME_EN. SMSC LAN89218 Section 3.5, "Wake-up Frame Detection," on page Table 3.11, all clocks to the MAC and host bus are disabled and the PHY is ...
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... High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Table 3.11 Power Management States D0 D1 (WOL) Full ON Full ON Full ON RX Power Mgmt. Block On Full ON OFF Full ON Full ON KEY CLOCK ON BLOCK DISABLED – CLOCK ON FULL OFF 50 DATASHEET Datasheet D2 (ENERGY DETECT) Energy Detect Power-Down OFF OFF OFF SMSC LAN89218 ...
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... This power-down is controlled by register 0, bit 11. In this mode the internal PHY, except the management interface, is powered-down and stays in that condition as long as Phy register bit 0.11 is HIGH. When bit 0.11 is cleared, the PHY powers up and is automatically reset. Please refer to 5.5.1, "Basic Control Register," on page 124 SMSC LAN89218 WOL_EN WUPS ED_EN ...
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... High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications for additional information on this register. In this mode when Section 5.5.11, "Interrupt Source Flag," on page NASR REGISTERS Note 3.13 MIL MAC Note 3. DATASHEET Datasheet Section 131. If the EEPROM MAC ADDR. CONFIG. PHY RELOAD STRAPS Note 3.12 LATCHED SMSC LAN89218 ...
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... APPLICATION NOTE: Following deassertion of a soft reset, the READY bit in PMT_CTRL will be set (high -”1”) within 2 μs. If the software driver polls this bit and it is not set within 100 ms, then an error condition occurred. SMSC LAN89218 Section 7.2, "Operating Conditions**," on page 145 Section 6.8, "nRESET Timing," on page 143 for additional details. Section 6.8, " ...
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... The host can instruct the LAN89218 to issue an interrupt when the buffer has been fully loaded into the TX FIFO contained in the LAN89218 and transmitted. This feature is enabled through the TX command ‘Interrupt on Completion’ field. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 54 DATASHEET Datasheet SMSC LAN89218 ...
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... After writing the command, the host can then move the payload data into the TX FIFO. TX status DWORD’s are stored in the TX status FIFO to be read by the host at a later time upon completion of the data transmission onto the wire. Last Buffer in Packet Figure 3.20 Simplified Host TX Flow Diagram SMSC LAN89218 init Idle TX Status Available Read TX ...
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... Optional offset DWORDn Offset + Data DWORD0 . . . . . Last Data & PAD Optional Pad DWORD0 . . . Optional Pad DWORDn Last Figure 3.21 TX Buffer Format Format", shows the TX Buffer written into the LAN89218. It should be for a detailed explanation on calculating the 56 DATASHEET Datasheet 0 Section 3.12.5, SMSC LAN89218 ...
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... First Segment (FS). When set, this bit indicates that the associated buffer is the first segment of the packet. 12 Last Segment. When set, this bit indicates that the associated buffer is the last segment of the packet 11 Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility. SMSC LAN89218 Table 3.13 TX Command 'A' Format DESCRIPTION [25] [24] End Alignment 0 ...
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... If the Packet Length field does not match the actual number of bytes in the packet the Transmitter Error (TXE) flag will be set. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications DESCRIPTION Table 3.14 TX Command 'B' Format DESCRIPTION Register, the TX checksum offload engine (TXCOE) 58 DATASHEET Datasheet SMSC LAN89218 ...
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... DWORD), would give a total space consumption of 2,032 bytes, leaving 4 bytes to spare; this is the basis for the "86 fragment" rule mentioned above. SMSC LAN89218 Table 3.15, "TX DATA Start Table 3.15 TX DATA Start Offset ...
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... Reserved. This bit is reserved. Always write zero to this bit to guarantee future compatibility. 0 Deferred. When set, this bit indicates that the current packet transmission was deferred. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications DESCRIPTION 60 DATASHEET Datasheet SMSC LAN89218 ...
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... End Alignment” Buffer 1: 0-Byte “Data Start Offset” 15-Bytes of payload data 16-Byte “Buffer End Alignment” Buffer 2: 10-Byte “Data Start Offset” 17-Bytes of payload data 16-Byte “Buffer End Alignment” SMSC LAN89218 61 DATASHEET Revision 1.3 (02-23-10) ...
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... TX Command 'B' 10-Byte Data Start Offset 17-Byte Payload Data 5-Byte End Padding Figure 3.22 TX Example 1 62 DATASHEET Datasheet TX Data FIFO TX Command 'A' TX Command 'B' 79-Byte Payload TX Command 'A' 15-Byte Payload TX Command 'A' 17-Byte Payload NOTE: Extra bytes betw een buffers are not transmitted SMSC LAN89218 ...
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... Buffer End Alignment = 0 Data Start Offset = 6 First Segment = 1 Last Segment = 1 Buffer Size =183 TX Command 'B' Packet Length = 183 SMSC LAN89218 illustrates the TX command structure for this example, and also shows Data Written to the 0 TX Command 'A' TX Command 'B' 6-Byte Data Start Offset 183-Byte Payload Data 3B End Padding Figure 3 ...
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... COE_CR register. For more information, refer to Checksum Offload Engine Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications illustrates the TX command structure for this example, and also shows (TXCOE)". 64 DATASHEET Datasheet Section 3.6.2, "Transmit SMSC LAN89218 ...
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... Data Start Offset = 10 First Segment = 0 Last Segment = 1 Buffer Size = 17 TX Command 'B' Packet Length = 115 TX Checksum Enable = 1 SMSC LAN89218 NOTE: When enabled, the TX Checksum transmitted. The FS bit in TX Command 'A', the 0 CK bit in TX Command 'B' and the TXCOE_EN TX Command 'A' bit in the COE_CR register must all be set for the TX checksum to be generated ...
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... Once a packet has been padded by the H/ the responsibility of the host to interrogate the Packet length field in the RX status and determine how much padding to discard at the end of the Packet. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 66 DATASHEET Datasheet SMSC LAN89218 ...
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... The host should perform the proper number of reads, as indicated by the packet length plus the start offset and the amount of optional padding added to the end of the frame, from the RX data FIFO. Last Packet Figure 3.25 Host Receive Routine Using Interrupts Figure 3.26 Host Receive Routine with Polling SMSC LAN89218 init Idle RX Interrupt Read RX ...
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... Section 3.13.4, "Stopping and Starting the Receiver," on page on the RX_DUMP bit, please refer to page 91. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Section 5.3.7, "RX_CFG—Receive Configuration Register," DATASHEET Datasheet 71. For more information SMSC LAN89218 ...
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... RX Data FIFO. The RX checksum is enabled by setting the RXCOE_EN bit in the Control Register. For more information on the RX checksum, refer to Checksum Offload Engine Figure 3.28 RX Packet Format with RX Checksum SMSC LAN89218 Figure 3.27 assumed that the host has previously read the associated Host Read 31 Order ...
Page 70
... RX_ER pin is asserted during the reception of a frame even though the CRC may be correct. This bit is not valid if the received frame is a Runt frame late collision was detected or when the Watchdog Time-out occurs. 0 Reserved. These bits are reserved. Reads 0 Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications DESCRIPTION 70 DATASHEET Datasheet SMSC LAN89218 ...
Page 71
... If the Receiver Error (RXE) flag is asserted for any reason, the receiver will continue operation. RX Error (RXE) will be asserted under the following conditions: A host underrun of RX data FIFO A host underrun of the RX status FIFO An overrun of the RX status FIFO It is the duty of the host to identify and resolve any error conditions. SMSC LAN89218 71 DATASHEET Revision 1.3 (02-23-10) ...
Page 72
... Encoder 125 Mbps Serial MLT-3 Tx MLT-3 MLT-3 Converter Driver MLT-3 CAT-5 MLT-3 Figure 4.1 100Base-TX Data Path Figure 4.1. Each major block is explained below. 72 DATASHEET Datasheet Scrambler 25 MHz by 5 bits and PISO Magnetics Table 4.1. Each 4-bit data-nibble SMSC LAN89218 ...
Page 73
... INVALID, RX_ER if during RX_DV 11001 V INVALID, RX_ER if during RX_DV 00000 V INVALID, RX_ER if during RX_DV 00001 V INVALID, RX_ER if during RX_DV 00010 V INVALID, RX_ER if during RX_DV SMSC LAN89218 Table 4.1 4B/5B Code Table RECEIVER INTERPRETATION 0000 DATA 0001 0010 0011 0100 0101 0110 0111 ...
Page 74
... The transmitter drives into the 100 Ω impedance of the CAT-5 cable. Cable termination and impedance matching require external components. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Table 4.1 4B/5B Code Table (continued) RECEIVER INTERPRETATION 74 DATASHEET Datasheet TRANSMITTER INTERPRETATION INVALID INVALID INVALID INVALID INVALID SMSC LAN89218 ...
Page 75
... The 100M PLL generates multiple phases of the 125 MHz clock. A multiplexer, controlled by the timing unit of the DSP, selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to extract the serial data from the received signal. SMSC LAN89218 100M PLL ...
Page 76
... Manchester-encoded and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics. The 10M transmitter uses the following blocks: MII (digital) TX 10M (digital) 10M Transmitter (analog) 10M PLL (analog) Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 76 DATASHEET Datasheet SMSC LAN89218 ...
Page 77
... Manchester signal and from this, generates the received 20 MHz clock. Using this clock, the Manchester encoded data is extracted and converted MHz NRZI data stream then converted from serial to 4-bit wide parallel data. The RX10M block also detects valid 10Base-T IDLE signals - Normal Link Pulses (NLPs maintain the link. SMSC LAN89218 77 DATASHEET Revision 1.3 (02-23-10) ...
Page 78
... The 16 even-numbered pulses, which may be present or absent, contain the data word being transmitted. Presence of a data pulse represents a “1”, while absence represents a “0”. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 78 DATASHEET Datasheet SMSC LAN89218 ...
Page 79
... LAN89218 will respond by stopping all transmission/receiving operations. Once the break_link_timer is done, in the Auto-negotiation state-machine (approximately 1200ms) the auto-negotiation will re- start. The Link Partner will have also dropped the link due to lack of a received signal too will resume auto-negotiation. SMSC LAN89218 79 DATASHEET Revision 1.3 (02-23-10) ...
Page 80
... Transmitting Half-Duplex Receiving Full-Duplex Transmitting Full-Duplex Receiving Half-Duplex Transmitting Half-Duplex Receiving Full-Duplex Transmitting Full-Duplex Receiving 80 DATASHEET Datasheet Section 3.12.4, CRS BEHAVIOR (Note 4.1) Active Active Low Active Active Active Low Active Active Active Low Active Active Active Low Active SMSC LAN89218 ...
Page 81
... The figure below shows the signal names at the RJ-45 connector, The mapping of these signals to the pins on the LAN89218 is as follows: TXP = TPO+ TXN = TPO- RXP = TPI+ RXN = TPI- Figure 4.3 Direct Cable Connection vs. Cross-over Cable Connection SMSC LAN89218 Figure 4.3, the SMSC LAN89218 Auto-MDIX PHY is 81 DATASHEET Revision 1.3 (02-23-10) ...
Page 82
... TX Status FIFO PEEK 4Ch TX Status FIFO Port 48h RX Status FIFO PEEK 44h RX Status FIFO Port 40h 3Ch TX Data FIFO Alias Ports 24h TX Data FIFO Port 20h 1Ch RX Data FIFO Alias Ports 04h RX Data FIFO Port Figure 5.1 Memory Map 82 DATASHEET Datasheet SMSC LAN89218 ...
Page 83
... The RX Data FIFO has a single port; reading data from this port always causes the top of the RX Data FIFO to be “popped”. This port is aliased to 8 DWORD (in 32-bit mode DWORD locations (in 16-bit mode). The host may access the top of the RX Data FIFO through any of these locations. SMSC LAN89218 DESCRIPTION 83 DATASHEET Revision 1 ...
Page 84
... General Purpose Timer Configuration General Purpose Timer Count Reserved for future use WORD SWAP Register Free Run Counter 84 DATASHEET Datasheet DEFAULT See Page 85. 00000000h 00000000h 00000000h - 87654321h 48000000h 00000000h 00000000h 00050000h 00000000h 00000000h 00001200h 00000000h 00000000h 0000FFFFh 0000FFFFh - 00000000h - SMSC LAN89218 ...
Page 85
... Chip ID. This read-only field identifies this design 15:0 Chip Revision Note 5.1 Default value is dependant on device revision. SMSC LAN89218 CONTROL AND STATUS REGISTERS REGISTER NAME RX Dropped Frames Counter MAC CSR Synchronizer Command (MAC CSR’s are indexed through this register) ...
Page 86
... When set, the IRQ output is a Push-Pull driver. When configured as an open-drain output the IRQ_POL field is ignored, and the interrupt output is always active low. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 54h Size: DESCRIPTION 86 DATASHEET Datasheet 32 bits TYPE DEFAULT R R R/W 0 NASR RO - R/W 0 NASR SMSC LAN89218 ...
Page 87
... Receiver Error (RXE). 14 error. Please refer to Section 3.13.5, "Receiver Errors," on page 71 description of the conditions that will cause an RXE. SMSC LAN89218 58h Size: DESCRIPTION his interrupt is issued when the receiver is T Generated when the TX Status ...
Page 88
... These interrupts are configured through the GPIO_CFG register. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications DESCRIPTION When generated, indicates that the Section 3.12.7, 66, for a description of the conditions that 88 DATASHEET Datasheet TYPE DEFAULT R/ R/WC 0 R/WC 0 R/WC 0 R/ R/WC 0 R/WC 0 R/WC 000 SMSC LAN89218 ...
Page 89
... TX Status FIFO Full Interrupt (TSFF_INT_EN Status FIFO Level Interrupt (TSFL_INT_EN Dropped Frame Interrupt Enable (RXDF_INT_EN) 5 Reserved 4 RX Status FIFO Full Interrupt (RSFF_INT_EN Status FIFO Level Interrupt (RSFL_INT_EN) 2:0 GPIO [2:0] (GPIOx_INT_EN). SMSC LAN89218 5Ch Size: DESCRIPTION 89 DATASHEET 32 bits TYPE DEFAULT R R/W ...
Page 90
... RX Status FIFO Level interrupt (RSFL) will be generated. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 64h Size: DESCRIPTION 68h Size: DESCRIPTION 90 DATASHEET Datasheet 32 bits TYPE DEFAULT RO 87654321h 32 bits TYPE DEFAULT R/W 48h R/W 00h RO - R/W 00h SMSC LAN89218 ...
Page 91
... RX is running. The receiver must be halted, and all data purged before these two bits can be modified. The upper three bits (DWORD offset) may be modified while the receiver is running. Modifications to the upper bits will take affect on the next DWORD read. 7:0 Reserved SMSC LAN89218 6Ch Size: DESCRIPTION for bit definitions 91 DATASHEET ...
Page 92
... All writes to this bit are ignored while this bit is high. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Table 5.2 RX Alignment Bit Definitions End Alignment 4-byte alignment 16-byte alignment 32-byte alignment Reserved 70h Size: DESCRIPTION 92 DATASHEET Datasheet 32 bits TYPE DEFAULT R SMSC LAN89218 ...
Page 93
... The host processor must correct the problem and issue another soft reset. SMSC LAN89218 74h Size: for details on stopping the transmitter and receiver. ...
Page 94
... Note: The RX data FIFO is considered full 4 DWORDs before the length that is specified in the HW_CFG register. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications DESCRIPTION for details on PHY reset 94 DATASHEET Datasheet TYPE DEFAULT SC 0 SMSC LAN89218 ...
Page 95
... RX and TX MIL FIFO levels are not visible to the host processor. RX and TX MIL FIFOs operate independent of the TX data and RX data and status FIFOs. FIFO levels set for the RX and TX data and Status FIFOs do not take into consideration the MIL FIFOs. SMSC LAN89218 Table 5.3 Valid TX/RX FIFO Allocations TX STATUS FIFO ...
Page 96
... DWORD (if the payload does not end on a DWORD boundary). Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 78h Size: DESCRIPTION 7Ch Size: DESCRIPTION 96 DATASHEET Datasheet 32 bits TYPE DEFAULT R bits TYPE DEFAULT 00h RO 0000h SMSC LAN89218 ...
Page 97
... PHY Reset (PHY_RST) – Writing a ‘1’ to this bit resets the PHY. The internal logic automatically holds the PHY reset for a minimum of 100 µs. When the PHY is released from reset, this bit is automatically cleared. All writes to this bit are ignored while this bit is high. SMSC LAN89218 80h Size: DESCRIPTION ...
Page 98
... READY bit is cleared. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications DESCRIPTION Figure 3.19 PME and 51. Section 3.10.2.3, "Power 51). 98 DATASHEET Datasheet TYPE DEFAULT R R/W 0b NASR R/WC 00 R/W 0b R/W 0b NASR R SMSC LAN89218 ...
Page 99
... GPIO Direction 0-2 (GPDIRn). When set, enables the corresponding GPIO as output. When cleared the GPIO is enabled as an input. GPIO0 – bit 8 GPIO1 – bit 9 GPIO2 – bit 10 7:5 Reserved SMSC LAN89218 88h Size: DESCRIPTION for the EEPROM Enable bit function definitions. 99 DATASHEET ...
Page 100
... High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications DESCRIPTION Table 5.4 EEPROM Enable Bit Definitions EEDIO FUNCTION EEDIO GPO3 GPO3 TX_EN TX_EN TX_CLK 100 DATASHEET Datasheet TYPE DEFAULT R/W 00 R/W 000 EECLK FUNCTION EECLK GPO4 Reserved RX_DV Reserved GPO4 RX_DV RX_CLK SMSC LAN89218 ...
Page 101
... GPT_CNT-General Purpose Timer Current Count Register Offset: This register reflects the current value of the GP Timer. BITS 31:16 Reserved 15:0 General Purpose Timer Current Count (GPT_CNT). This 16-bit field reflects the current value of the GP Timer. SMSC LAN89218 8Ch Size: DESCRIPTION 90h Size: DESCRIPTION 101 DATASHEET ...
Page 102
... Note: This counter will run regardless of the power management states D0 D2. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 98h Size: DESCRIPTION Section 3.7.4, "Mixed for more information. 9Ch Size: DESCRIPTION 102 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W 00000000h NASR 32 bits TYPE DEFAULT RO - SMSC LAN89218 ...
Page 103
... R/nW. When set, this bit indicates that the host is requesting a read operation. When clear, the host is performing a write. 29:8 Reserved. 7:0 CSR Address. The 8-bit value in this field selects which MAC CSR will be accessed with the read or write operation. SMSC LAN89218 A0h Size: DESCRIPTION A4h Size: DESCRIPTION ...
Page 104
... MAC CSR’s. BITS 31:0 MAC CSR Data. Value read from or written to the MAC CSR’s. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications A8h Size: DESCRIPTION 104 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W 00000000h SMSC LAN89218 ...
Page 105
... This field has no function in full-duplex mode. 1 Flow Control on Address Decode (FCADD). When this bit is set, the LAN89218 will assert back pressure when the AFC level is reached and a frame addressed to the LAN89218 is received. This field has no function in full-duplex mode. SMSC LAN89218 ACh Size: DESCRIPTION 105 DATASHEET ...
Page 106
... DATASHEET Datasheet TYPE DEFAULT R Mbps Mode 7.2 µs 12.2 µs 17.2 µs 27.2 µs 52.2 µs 102.2 µs 152.2 µs 202.2 µs 252.2 µs 302.2 µs 352.2 µs 402.2 µs 452.2 µs 502.2 µs 552.2 µs 602.2 µs SMSC LAN89218 ...
Page 107
... EPC Busy remains busy until the EPC Time-out occurs. At that time the busy bit is cleared. Note: EPC busy will be high immediately following power-up or reset. After the EEPROM controller has finished reading (or attempting to read) the MAC address from the EEPROM the EPC Busy bit is cleared. SMSC LAN89218 B0h Size: DESCRIPTION 107 ...
Page 108
... Address Loaded” bit indicates a successful load of the MAC address. 27:10 Reserved Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications DESCRIPTION [28] OPERATION 0 0 READ 0 1 EWDS 1 0 EWEN 1 1 WRITE 0 0 WRAL 0 1 ERASE 1 0 ERAL 1 1 Reload 108 DATASHEET Datasheet TYPE DEFAULT R SMSC LAN89218 ...
Page 109
... This register is used in conjunction with the E2P_CMD register to perform read and write operations with the Serial EEPROM. BITS 31:8 Reserved 7:0 EEPROM Data. Value read from or written to the EEPROM. SMSC LAN89218 DESCRIPTION When set, this bit indicates that a valid EEPROM B4h Size: DESCRIPTION 109 ...
Page 110
... Multicast Hash Table Low MII Access MII Data Flow Control VLAN1 Tag VLAN2 Tag Wake-up Frame Filter Wake-up Control and Status Checksum Offload Engine Control 110 DATASHEET Datasheet DEFAULT 00040000h 0000FFFFh FFFFFFFFh 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h SMSC LAN89218 ...
Page 111
... Pass Bad Frames (PASSBAD). When set, all incoming frames that passed address filtering are received, including runt frames and collided frames. 15 Hash Only Filtering mode (HO). When set, the address check Function operates in the Imperfect Address Filtering mode both for physical and multicast addresses 14 Reserved SMSC LAN89218 1 Attribute: 00040000h Size: DESCRIPTION 111 ...
Page 112
... Note: When PADSTR is enabled, the RX Checksum Offload Engine must be disabled (bit 0 (RXCOE_EN) of the These functions cannot be enabled simultaneously. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications DESCRIPTION COE_CR—Checksum Offload Engine Control 112 DATASHEET Datasheet WUCSR—Wake-up Control Register) and vice versa. SMSC LAN89218 ...
Page 113
... Receiver Enable (RXEN). When set (1), the MAC’s receiver is enabled and will receive frames from the internal PHY. When reset, the MAC’s receiver is disabled and will not receive any frames from the internal PHY. 1:0 Reserved SMSC LAN89218 DESCRIPTION BOLMT Value # Bits Used from LFSR Counter 2’b00 2’ ...
Page 114
... The host can update the contents of this field after the initialization process has completed. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 2 Attribute: 0000FFFFh Size: Section 4.6 for more information on the EEPROM. Section DESCRIPTION 114 DATASHEET Datasheet R/W 32 bits 5.4.3 SMSC LAN89218 ...
Page 115
... Figure 5.2 Example ADDRL, ADDRH and EEPROM Setup Note: By convention, the left most byte of the Ethernet address (in this example 0x12) is the most significant byte and is transmitted/received first. SMSC LAN89218 3 Attribute: FFFFFFFFh Size: Section 4.6 for more information on the EEPROM. ...
Page 116
... Lower 32 bits of the 64-bit Hash Table Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 4 Attribute: 00000000h Size: DESCRIPTION 5 Attribute: 00000000h Size: for further details. DESCRIPTION 116 DATASHEET Datasheet R/W 32 bits R/W 32 bits Table 5.4.4, SMSC LAN89218 ...
Page 117
... Register, or the read data from the PHY register whose index is specified in the MII Access Register. BITS 31:16 Reserved 15:0 MII Data. This contains the 16-bit value read from the PHY read operation or the 16-bit data value to be written to the PHY before an MII write operation. SMSC LAN89218 6 Attribute: 00000000h Size: DESCRIPTION 7 ...
Page 118
... Notes: When writing this register the FCBSY bit must always be zero. Applications must always write a zero to this bit Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 8 Attribute: 00000000h Size: DESCRIPTION 118 DATASHEET Datasheet R/W 32 bits SMSC LAN89218 ...
Page 119
... VLAN2 Tag Identifier (VTI2). This contains the VLAN Tag field to identify the VLAN2 frames. This field is compared with the 13th and 14th bytes of the incoming frames for VLAN2 frame detection.If used, this register must be set to 0x8100. SMSC LAN89218 9 Attribute: 00000000h ...
Page 120
... WFF pointers if it has not previously read/written the complete contents of the WFF. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications B Attribute: 00000000h Size: DESCRIPTION WUCSR—Wake-up Control and Status 120 DATASHEET Datasheet R/W 32 bits Register. This SMSC LAN89218 ...
Page 121
... Wake-Up Frame enabled (WUEN). When set, Remote Wake-Up mode is enabled and the MAC is capable of detecting wake-up frames as programmed in the wake-up frame filter. 1 Magic Packet Enable (MPEN). When set, Magic Packet Wake-up mode is enabled. 0 Reserved SMSC LAN89218 C Attribute: 00000000h Size: DESCRIPTION 121 ...
Page 122
... Note: When the RXCOE is enabled, automatic pad stripping must be disabled (bit 8 (PADSTR) of the MAC_CR—MAC Control simultaneously. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications D Attribute: 00000000h Size: DESCRIPTION Register) and vice versa. These functions cannot be enabled 122 DATASHEET Datasheet R/W 32 bits SMSC LAN89218 ...
Page 123
... Auto-Negotiation Link Partner Ability Register 6 Auto-Negotiation Expansion Register 17 Mode Control/Status Register 18 Special Modes Register 27 Special Control/Status Indications 29 Interrupt Source Register 30 Interrupt Mask Register 31 PHY Special Control/Status Register SMSC LAN89218 Table 5.8, "LAN89218 PHY Control and Status 123 DATASHEET Register". Revision 1.3 (02-23-10) ...
Page 124
... Note 5.2 The default value of this bit is determined by Pin 74 "SPEED_SEL". Please refer to the pin description section for more details. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 0 Size: DESCRIPTION 124 DATASHEET Datasheet 16-bits TYPE DEFAULT RW/ See Note 5.2 RW See Note 5 RW/ SMSC LAN89218 ...
Page 125
... Extended Capabilities supports extended capabilities registers 0 = does not support extended capabilities registers. 5.5.3 PHY Identifier 1 Index (In Decimal): BITS 15:0 PHY ID Number. Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. SMSC LAN89218 1 Size: DESCRIPTION 2 Size: DESCRIPTION 125 DATASHEET ...
Page 126
... High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 3 Size: DESCRIPTION 4 Size: DESCRIPTION Note 5.3) 126 DATASHEET Datasheet 16-bits TYPE DEFAULT RO 0xC0C3h RO RO 16-bits TYPE DEFAULT RO 00 R/W 0 R R/W See Note 5.4 R/W 1 R/W See Note 5.4 R/W See Note 5.4 R/W 00001 SMSC LAN89218 ...
Page 127
... Full Duplex with full duplex full duplex ability 7 100Base-TX able ability 6 10Base-T Full Duplex Mbps with full duplex Mbps with full duplex ability 5 10Base- Mbps able Mbps ability 4:0 Selector Field. [00001] = IEEE 802.3 SMSC LAN89218 5 Size: DESCRIPTION 127 DATASHEET 16-bits TYPE DEFAULT ...
Page 128
... Note 5.5 The default value of this bit will vary dependant on the current link state of the line. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 6 Size: DESCRIPTION 17 Size: DESCRIPTION 128 DATASHEET Datasheet 16-bits TYPE DEFAULT RO 0 RO/ RO/ 16-bits TYPE DEFAULT See Note 5 SMSC LAN89218 ...
Page 129
... Reserved - Do not set the LAN89218 in this mode. 111 All capable. Auto-negotiation enabled. Note 5.6 When MODE=111, the register 0 bits 13 and 8 are variable dependant on the auto-negotiated speed and duplex. SMSC LAN89218 18 Size: DESCRIPTION Table 5.9 for more details. Table 5.9 MODE Control ...
Page 130
... XPOL: Polarity state of the 10Base- Normal polarity 1 - Reversed polarity 3:0 Reserved: Read only - Writing to these bits have no effect. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 27 Size: DESCRIPTION 130 DATASHEET Datasheet 16-bits MODE DEFAULT RW, 0 NASR XXXXb SMSC LAN89218 ...
Page 131
... Note 5.7 The default value of this bit will vary dependant on the current link state of the line. 5.5.12 Interrupt Mask Index (In Decimal): BITS 15:8 Reserved. Write as 0; ignore on read. 7:0 Mask Bits interrupt source is enabled 0 = interrupt source is masked SMSC LAN89218 29 Size: DESCRIPTION 30 Size: DESCRIPTION 131 DATASHEET ...
Page 132
... Note 5.8 See Table 2.5, “Default Ethernet Settings,” on page Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications 31 Size: DESCRIPTION 21, for default settings. 132 DATASHEET Datasheet 16-bits TYPE DEFAULT RO 000b 0000010b RO See Note 5.8 RO 00b SMSC LAN89218 ...
Page 133
... Note that dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met. SMSC LAN89218 Section 7.2, "Operating Table 6.1, "Read After Write Timing Table 6 ...
Page 134
... High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Table 6.1 Read After Write Timing Rules MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS) 0 135 135 315 45 45 135 45 180 134 DATASHEET Datasheet NUMBER OF BYTE_TEST READS (ASSUMING NS) CYCLE SMSC LAN89218 ...
Page 135
... WAIT FOR THIS MANY READING... NS… RX Data FIFO RX Status FIFO TX Status FIFO RX_DROP SMSC LAN89218 Table 6.2, "Read After Read Timing Table 6.2 also shows the number of dummy reads that are Table 6.2 Read After Read Timing Rules OR PERFORM THIS MANY READS OF BYTE_TEST… ...
Page 136
... They may be asserted and deasserted in any order. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications t cycle t asu t csl t csdv t don Figure 6.1 PIO Read Cycle Timing Table 6.3 PIO Read Timing 136 DATASHEET Datasheet csh t doff t doh MIN TYP MAX UNITS SMSC LAN89218 ...
Page 137
... Data Output Hold Time doh Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and deasserted in any order. SMSC LAN89218 t t acyc acyc ...
Page 138
... They may be asserted and de- asserted in any order. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications t cycle t asu t csl t csdv t t doh don MIN 138 DATASHEET Datasheet csh t doff TYP MAX UNITS SMSC LAN89218 ...
Page 139
... Data Bus Figure 6.4 RX Data FIFO Direct PIO Burst Read Cycle Timing Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths. SMSC LAN89218 t acyc t t csdv adv adv 139 DATASHEET ...
Page 140
... Note Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and deasserted in any order. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications MIN 140 DATASHEET Datasheet TYP MAX UNITS SMSC LAN89218 ...
Page 141
... Data Setup to nCS, nWR Deassertion dsu t Data Hold Time dh Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either or both nCS and nWR are deasserted. They may be asserted and deasserted in any order. SMSC LAN89218 t cycle t asu t csl ...
Page 142
... They may be asserted and deasserted in any order. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications t cycle t asu t csl t dsu 142 DATASHEET Datasheet csh t dh MIN TYP MAX UNITS SMSC LAN89218 ...
Page 143
... Configuration strap pins setup to nRESET deassertion css t Configuration strap pins hold after nRESET deassertion csh Note: Device configuration straps are latched as a result of nRESET assertion. SMSC LAN89218 for additional information. t rstia t t css csh Figure 6.7 nRESET Reset Pin Timing ...
Page 144
... Figure 6.8 EEPROM Timing Table 6.10 EEPROM Timing Values MIN 1110 550 550 1070 30 550 550 90 0 580 0 1070 144 DATASHEET Datasheet t csl t cklcsl t ckldis t dhcsl TYP MAX UNITS 1130 ns 570 ns 570 600 SMSC LAN89218 ...
Page 145
... LAN89218 is guaranteed only within the ranges specified in this section. 7.3 Package Thermal Specifications PARAMETER SYMBOL Thermal Resistance Junction-to-Top-of-Package Note: Thermal parameters are measured or estimated for devices in a multilayer 2S2P PCB per JESD51. SMSC LAN89218 (Note (Note Table 7.1 Package Thermal Parameters VALUE UNITS o Θ 35 ...
Page 146
... D2, General Power Down Note 7 Normal Operation WOL (Wake On LAN mode), D2= Low Power Energy Detect. Revision 1.3 (02-23-10) High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications MODE 146 DATASHEET Datasheet Total Power - Typical (mW) 295 290 175 64 12 420 415 300 64 12 SMSC LAN89218 ...
Page 147
... MODE 10BASE-T Operation D0, 10BASE-T /w traffic D0, Idle D1, Idle D2, Energy Detect Power Down D2, General Power Down 100BASE-TX Operation D0, 100BASE-TX /w traffic D0, Idle D1, Idle D2, Energy Detect Power Down D2, General Power Down SMSC LAN89218 Total Power - Typical (mW) 147 DATASHEET 655 650 535 64 12 565 560 445 64 12 Revision 1 ...
Page 148
... Table 7.4 Supply Current Characteristics MIN TYP MAX Table 7.5 I/O Buffer Characteristics MIN TYP MAX -0.3 2.0 -10 IN 148 DATASHEET Datasheet UNITS NOTES UNITS NOTES 0 Measured between V and V ILI 10 µA Note 7.5 750 µA Note 7.5, Note 7.6 3.3 pF SMSC LAN89218 IHI ...
Page 149
... Note 7.5 This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down and pull-up resistors add ± 50µA per-pin (typical). Note 7.6 This is the total V number of pins driven to V driven to the maximum operational limit for V input leakage current divided by 10. SMSC LAN89218 MIN TYP MAX 0.9 1.2 1 ...
Page 150
... RFS D ±250 CD V 4.2 OS 1.4 SYMBOL MIN TYP MAX V 2.2 2.5 2.8 OUT V 516 DS 150 DATASHEET Datasheet UNITS NOTES mVpk Note 7.7 mVpk Note 7.7 % Note 7.7 ns Note 7.7 ns Note 7.7 ps Note 7 Note 7.9 UNITS NOTES V Note 7.10 mV SMSC LAN89218 ...
Page 151
... The XTAL1/CLKIN and XTAL2 pin and PCB capacitance values are required to accurately calculate the value of the two external load capacitors. These two external load capacitors determine the accuracy of the 25.000 MHz frequency. SMSC LAN89218 Table 7.8, "LAN89218 Crystal Specifications" SYMBOL ...
Page 152
... Lead Frame Thickness 0. 0.27 ~ Lead Shoulder Radius 0.20 0.08 152 DATASHEET Datasheet REMARKS Standoff Body Thickness X Span X body Size Y Span Y body Size Lead Foot Length Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Foot Radius Coplanarity SMSC LAN89218 ...
Page 153
... Section 7.4, "Power Consumption (Device Only)," on page 146 Section 7.5, "Power Consumption (Device and System Components)," on page 147 SMSC LAN89218 Table 9.1 Customer Revision History Diagram removed. Refer to On Reset (POR)," on page 53 Added application note regarding configuration strap timing requirements Fixed diagram error ...
Page 154
... Disable Broadcast Frame (BCAST) bit in the MAC_CR—MAC Control Fixed typo in bit 9: “... Mac Address [1:0] bit set to 0.” was changed to “...Mac Address [0] bit set to 0.” Fixed various typos 154 DATASHEET Datasheet CORRECTION WUCSR—Wake- Register, a broadcast wake- Register.” SMSC LAN89218 ...
Page 155
... High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications Datasheet Chapter 10 Further Information For more information on SMSC automotive products, including integrated circuits, software, and MOST development tools and modules, visit our web site: http://www.smsc-ais.com. Direct contact information is available at: http://www.smsc-ais.com/offices. ...