LAN89218AQ SMSC, LAN89218AQ Datasheet - Page 57

• Manufacturer Part Number: LAN89218AQ
• Description: Ethernet ICs High Perform Chip 10/100 NonPCI Cntrl
• Manufacturer: SMSC

Specifications of LAN89218AQ

• Ethernet Connection Type: 10BASE-T, 100BASE-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE802.3, IEEE802.3u
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
Datasheet
SMSC LAN89218
3.12.2
3.12.2.1
30:26
25:24
23:21
20:16
15:14
BITS
31
13
12
11
TX Command Format
The TX command instructs the TX FIFO controller on handling the subsequent buffer. The command
precedes the data to be transmitted. The TX command is divided into two, 32-bit words; TX command
‘A’ and TX command ‘B’.
There is a 16-bit packet tag in the TX command ‘B’ command word. Packet tags may, if host software
desires, be unique for each packet (i.e., an incrementing count). The value of the tag will be returned
in the RX status word for the associated packet. The Packet tag can be used by host software to
uniquely identify each status word as it is returned to the host.
Both TX command ‘A’ and TX command ‘B’ are required for each buffer in a given packet. TX
command ‘B’ must be identical for every buffer in a given packet. If the TX command ‘B’ words do not
match, the Ethernet controller will assert the Transmitter Error (TXE) flag.
TX Command ‘A’
Interrupt on Completion. When set, the TXDONE flag will be asserted when the current buffer has
been fully loaded into the TX FIFO. This flag may be optionally mapped to a host interrupt.
Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility.
Buffer End Alignment. This field specifies the alignment that must be maintained on the last data
transfer of a buffer. The host will add extra DWORDs of data up to the alignment specified in the
table below. The LAN89218 will remove the extra DWORDs. This mechanism can be used to
maintain cache line alignment on host processors.
Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility
Data Start Offset (bytes). This field specifies the offset of the first byte of TX data. The offset value
can be anywhere from 0 bytes to 31 a Byte offset.
Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility
First Segment (FS). When set, this bit indicates that the associated buffer is the first segment of the
packet.
Last Segment. When set, this bit indicates that the associated buffer is the last segment of the
packet
Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility.
[25]
0
0
1
1
Table 3.13 TX Command 'A' Format
[24]
DATASHEET
0
1
0
1
DESCRIPTION
57
16-byte alignment
32-byte alignment
4-byte alignment
End Alignment
Reserved
Revision 1.3 (02-23-10)