LAN89218AQ SMSC, LAN89218AQ Datasheet - Page 93

• Manufacturer Part Number: LAN89218AQ
• Description: Ethernet ICs High Perform Chip 10/100 NonPCI Cntrl
• Manufacturer: SMSC

Specifications of LAN89218AQ

• Ethernet Connection Type: 10BASE-T, 100BASE-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE802.3, IEEE802.3u
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Single-Chip 10/100 Ethernet Controller for Automotive Applications
Datasheet
SMSC LAN89218
5.3.9
31:25
23:21
19:16
BITS
15:3
24
20
2
1
Reserved
AMDIX_EN Strap State. This read-only bit reflects the state of the
AMDIX_EN strap pin (pin 73). This pin can be overridden by PHY Registers
27.15 and 27.13
Reserved
Must Be One (MBO). This bit must be set to “1” for normal device
operation.
TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1 kB values
to a maximum of 14 kB. The TX Status FIFO consumes 512 bytes of the
space allocated by TX_FIF_SIZ, and the TX data FIFO consumes the
remaining space specified by TX_FIF_SZ. The minimum size of the TX
FIFOs is 2 kB (TX data and status combined). The TX data FIFO is used
for both TX data and TX commands.
The RX status and data FIFOs consume the remaining space, which is
equal to 16 kB – TX_FIF_SIZ. See
Configurable FIFO Memory Allocation," on page 94
Reserved
32/16-bit Mode. When set, the LAN89218 is set for 32-bit operation. When
clear, it is configured for 16-bit operation. This field is the value of the
D32/nD16 strap.
Soft Reset Time-out (SRST_TO). If a software reset is attempted when the
internal PHY is not in the operational state (RX_CLK and TX_CLK running),
the reset will not complete and the soft reset operation will time-out and this
bit will be set to a ‘1’. The host processor must correct the problem and
issue another soft reset.
HW_CFG—Hardware Configuration Register
Note: The transmitter and receiver must be stopped before writing to this register. Refer to
Offset:
3.12.8, "Stopping and Starting the Transmitter," on page 66
Starting the Receiver," on page 71
DESCRIPTION
74h
Section 5.3.9.1, "Allowable Settings for
DATASHEET
93
for details on stopping the transmitter and receiver.
for more information.
Size:
and
32 bits
Section 3.13.4, "Stopping and
TYPE
R/W
R/W
RO
RO
RO
RO
RO
RO
Revision 1.3 (02-23-10)
DEFAULT
AMDIX
Strap
Pin
5h
0
0
-
-
-
Section